mlsanityData to 7 Oct 2026

Enhancing LUT-based Deep Neural Networks Inference through Architecture and Connectivity Optimization

arXiv 2601.09773 ↗First posted 14 Jan 2026cs.AR cs.AIcited by 0

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Abstract (arXiv)

Deploying deep neural networks (DNNs) on resource-constrained edge devices such as FPGAs requires a careful balance among latency, power, and hardware resource usage, while maintaining high accuracy. Existing Lookup Table (LUT)-based DNNs -- such as LogicNets, PolyLUT, and NeuraLUT -- face two critical challenges: the exponential growth of LUT size and inefficient random sparse connectivity. This paper presents SparseLUT, a comprehensive framework that addresses these challenges through two orthogonal optimizations. First, we propose an architectural enhancement that aggregates multiple PolyLUT sub-neurons via an adder, significantly reducing LUT consumption by 2.0x-13.9x and lowering inference latency by 1.2x-1.6x, all while maintaining comparable accuracy. Building upon this foundation, we further introduce a non-greedy training algorithm that optimizes neuron connectivity by selectively pruning less significant inputs and strategically regrowing more effective ones. This training optimization, which incurs no additional area and latency overhead, delivers consistent accuracy improvements across benchmarks -- achieving up to a 2.13% gain on MNIST and 0.94% on Jet Substructure Classification compared to existing LUT-DNN approaches.

Key facts. No citing papers in the map yet (data through 7 Oct 2026). Builds on 22 of its 41 references that are in the map. First posted on arXiv 14 Jan 2026.

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22 of 41 references.

References · 22

  1. 2019PyTorch: An Imperative Style, High-Performance Deep Learning Librarycited by 20,160
  2. 2013Network In Networkcited by 600
  3. 2017To prune, or not to prune: exploring the efficacy of pruning for model compressioncited by 596
  4. 2017Learning Sparse Neural Networks through L0 Regularizationcited by 571
  5. 2019Rigging the Lottery: Making All Tickets Winnerscited by 491
  6. 2019The State of Sparsity in Deep Neural Networkscited by 471
  7. 2017Variational Dropout Sparsifies Deep Neural Networkscited by 265
  8. 2017Deep Rewiring: Training very sparse deep networkscited by 136
  9. 2018Fast inference of deep neural networks in FPGAs for particle physicscited by 132
  10. 2019A Survey of Optimization Methods from a Machine Learning Perspectivecited by 90
  11. 2020Automatic heterogeneous quantization of deep neural networks for low-latency inference on the edge for particle detectorscited by 78
  12. 2021hls4ml: An Open-Source Codesign Workflow to Empower Scientific Low-Power Machine Learning Devicescited by 61
10 more
  1. 2020LogicNets: Co-Designed Neural Networks and Circuits for Extreme-Throughput Applicationscited by 55
  2. 2020Compressing deep neural networks on FPGAs to binary and ternary precision with HLS4MLcited by 42
  3. 2023Dynamic Sparse Training with Structured Sparsitycited by 36
  4. 2023PolyLUT: Learning Piecewise Polynomials for Ultra-Low Latency FPGA LUT-based Inferencecited by 30
  5. 2024Differentiable Weightless Neural Networkscited by 27
  6. 2024NeuraLUT: Hiding Neural Network Density in Boolean Synthesizable Functionscited by 21
  7. 2025TreeLUT: An Efficient Alternative to Deep Neural Networks for Inference Acceleration Using Gradient Boosted Decision Treescited by 15
  8. 2025NeuraLUT-Assemble: Hardware-aware Assembling of Sub-Neural Networks for Efficient LUT Inferencecited by 14
  9. 2024PolyLUT-Add: FPGA-based LUT Inference with Wide Inputscited by 12
  10. 2025PolyLUT: Ultra-low Latency Polynomial Inference with Hardware-Aware Structured Pruningcited by 8

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