Data to 7 Oct 2026

Gemmini: Enabling Systematic Deep-Learning Architecture Evaluation via Full-Stack Integration

arXiv 1911.09925 ↗First posted 22 Nov 2019cs.DC cs.AR cs.LGcited by 59

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Abstract (arXiv)

DNN accelerators are often developed and evaluated in isolation without considering the cross-stack, system-level effects in real-world environments. This makes it difficult to appreciate the impact of System-on-Chip (SoC) resource contention, OS overheads, and programming-stack inefficiencies on overall performance/energy-efficiency. To address this challenge, we present Gemmini, an open-source*, full-stack DNN accelerator generator. Gemmini generates a wide design-space of efficient ASIC accelerators from a flexible architectural template, together with flexible programming stacks and full SoCs with shared resources that capture system-level effects. Gemmini-generated accelerators have also been fabricated, delivering up to three orders-of-magnitude speedups over high-performance CPUs on various DNN benchmarks. * https://github.com/ucb-bar/gemmini

Key facts. Cited by 59 papers in the map (data through 7 Oct 2026). First posted on arXiv 22 Nov 2019.

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Citing papers per year: 2021: 1; 2022: 5; 2023: 10; 2024: 10; 2025: 22; 2026: 11.

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2023Full Stack Optimization of Transformer Inference: a Surveycited by 79
2023DiffRate : Differentiable Compression Rate for Efficient Vision Transformerscited by 78
2024LLMServingSim: A HW/SW Co-Simulation Infrastructure for LLM Inference Serving at Scalecited by 30
2025Embodied AI: From LLMs to World Modelscited by 23
2023A Survey on Deep Learning Hardware Accelerators for Heterogeneous HPC Platformscited by 21
2024Allo: A Programming Model for Composable Accelerator Designcited by 16
2023A Hardware Evaluation Framework for Large Language Model Inferencecited by 14
2024HiVeGen -- Hierarchical LLM-based Verilog Generation for Scalable Chip Designcited by 13
2025Autocomp: A Powerful and Portable Code Optimizer for Tensor Acceleratorscited by 12
2022CFU Playground: Full-Stack Open-Source Framework for Tiny Machine Learning (tinyML) Acceleration on FPGAscited by 11
2023MoCA: Memory-Centric, Adaptive Execution for Multi-Tenant Deep Neural Networkscited by 8
2024LLM-Aided Compilation for Tensor Acceleratorscited by 8

38 more

2025LUT-DLA: Lookup Table as Efficient Extreme Low-Bit Deep Learning Acceleratorcited by 8
2022Machine Learning Sensorscited by 5
2024MATCH: Model-Aware TVM-based Compilation for Heterogeneous Edge Devicescited by 5
2024Iterative Filter Pruning for Concatenation-based CNN Architecturescited by 4
2025DOSA: Differentiable Model-Based One-Loop Search for DNN Acceleratorscited by 4
2021GNNIE: GNN Inference Engine with Load-balancing and Graph-Specific Cachingcited by 3
2022Integration of a systolic array based hardware accelerator into a DNN operator auto-tuning frameworkcited by 3
2025Leveraging Compute-in-Memory for Efficient Generative Model Inference in TPUscited by 3
2026Economy of Minds: Emerging Multi-Agent Intelligence with Economic Interactionscited by 3
2022QUIDAM: A Framework for Quantization-Aware DNN Accelerator and Model Co-Explorationcited by 2
2023An Open-Source ML-Based Full-Stack Optimization Framework for Machine Learning Acceleratorscited by 2
2024MVQ:Towards Efficient DNN Compression and Acceleration with Masked Vector Quantizationcited by 2
2025TPU-Gen: LLM-Driven Custom Tensor Processing Unit Generatorcited by 2
2025An Open-Source HW-SW Co-Development Framework Enabling Efficient Multi-Accelerator Systemscited by 2
2022Hardware/Software Co-Programmable Framework for Computational SSDs to Accelerate Deep Learning Service on Large-Scale Graphscited by 1
2023Tackling the Matrix Multiplication Micro-kernel Generation with Exocited by 1
2024Efficient Edge AI: Deploying Convolutional Neural Networks on FPGA with the Gemmini Acceleratorcited by 1
2024HAPM -- Hardware Aware Pruning Method for CNN hardware accelerators in resource constrained devicescited by 1
2025FORTALESA: Fault-Tolerant Reconfigurable Systolic Array for DNN Inferencecited by 1
2025Beyond Moore's Law: Harnessing the Redshift of Generative AI with Effective Hardware-Software Co-Designcited by 1
2025HDLxGraph: Bridging Large Language Models and HDL Repositories via HDL Graph Databasescited by 1
2025MAHL: Multi-Agent LLM-Guided Hierarchical Chiplet Design with Adaptive Debuggingcited by 1
2025LEGO: Spatial Accelerator Generation and Optimization for Tensor Applicationscited by 1
2025FaRAccel: FPGA-Accelerated Defense Architecture for Efficient Bit-Flip Attack Resilience in Transformer Modelscited by 1
2026NLI:Non-uniform Linear Interpolation Approximation of Nonlinear Operations for Efficient LLMs Inferencecited by 1
2026AI+HW 2035: Shaping the Next Decadecited by 1
2026HighTide: An Agent-Curated Open-Source VLSI Benchmark Suitecited by 1
2023Performance Analysis of DNN Inference/Training with Convolution and non-Convolution Operationscited by 0
2023A Survey on Design Methodologies for Accelerating Deep Learning on Heterogeneous Architecturescited by 0
2023DEAP: Design Space Exploration for DNN Accelerator Parallelismcited by 0
2024Tempus Core: Area-Power Efficient Temporal-Unary Convolution Core for Low-Precision Edge DLAscited by 0
2025NVR: Vector Runahead on NPUs for Sparse Memory Accesscited by 0
2025CaMDN: Enhancing Cache Efficiency for Multi-tenant DNNs on Integrated NPUscited by 0
2025FlexiSAGA: A Flexible Systolic Array GEMM Accelerator for Sparse and Dense Processingcited by 0
2025A High-Level Compiler Integration Approach for Deep Learning Accelerators Supporting Abstraction and Optimizationcited by 0
2025FedChip: Federated LLM for Artificial Intelligence Accelerator Chip Designcited by 0
2025Energy Efficient Exact and Approximate Systolic Array Architecture for Matrix Multiplicationcited by 0
2025Systematic Exploration of Multi-core Architectures for Efficient LLM Serving using WaferAI-SIMcited by 0

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