mlsanityData to 7 Oct 2026

LHNN: Lattice Hypergraph Neural Network for VLSI Congestion Prediction

arXiv 2203.12831 ↗First posted 24 Mar 2022cs.LGcited by 18

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Abstract (arXiv)

Precise congestion prediction from a placement solution plays a crucial role in circuit placement. This work proposes the lattice hypergraph (LH-graph), a novel graph formulation for circuits, which preserves netlist data during the whole learning process, and enables the congestion information propagated geometrically and topologically. Based on the formulation, we further developed a heterogeneous graph neural network architecture LHNN, jointing the routing demand regression to support the congestion spot classification. LHNN constantly achieves more than 35% improvements compared with U-nets and Pix2Pix on the F1 score. We expect our work shall highlight essential procedures using machine learning for congestion prediction.

Key facts. Cited by 18 papers in the map (data through 7 Oct 2026). Builds on 6 of its 21 references that are in the map. First posted on arXiv 24 Mar 2022.

Builds on

6 of 21 references.

References · 6

  1. 2015U-Net: Convolutional Networks for Biomedical Image Segmentationcited by 19,604
  2. 2016Image-to-Image Translation with Conditional Adversarial Networkscited by 4,510
  3. 2017Neural Message Passing for Quantum Chemistrycited by 3,460
  4. 2017Modeling Relational Data with Graph Convolutional Networkscited by 1,684
  5. 2020Heterogeneous Graph Transformercited by 581
  6. 2019Deep Graph Library: A Graph-Centric, Highly-Performant Package for Graph Neural Networkscited by 241

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Cited by year (2026 to 7 Oct)

Citing papers per year: 2023: 4; 2024: 6; 2025: 6; 2026: 2.

18 papers.

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  1. 2023Learnable Behavior Control: Breaking Atari Human World Records via Sample-Efficient Behavior Selectioncited by 14
  2. 2024DE-HNN: An effective neural model for Circuit Netlist representationcited by 7
  3. 2023A Circuit Domain Generalization Framework for Efficient Logic Synthesis in Chip Designcited by 6
  4. 2024PreRoutGNN for Timing Prediction with Order Preserving Partition: Global Circuit Pre-training, Local Delay Learning and Attentional Cell Modelingcited by 5
  5. 2024Chip Placement with Diffusion Modelscited by 5
  6. 2023Circuit as Set of Pointscited by 3
  7. 2025VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Codecited by 3
  8. 2025DICE: Device-level Integrated Circuits Encoder with Graph Contrastive Pretrainingcited by 2
  9. 2024A Lightweight Inception Boosted U-Net Neural Network for Routability Predictioncited by 1
  10. 2024RoutePlacer: An End-to-End Routability-Aware Placer with Graph Neural Networkcited by 1
  11. 2025DR-CircuitGNN: Training Acceleration of Heterogeneous Circuit Graph Neural Network on GPUscited by 1
  12. 2023Variational Label-Correlation Enhancement for Congestion Predictioncited by 0
6 more
  1. 2024Improving Routability Prediction via NAS Using a Smooth One-shot Augmented Predictorcited by 0
  2. 2025TransPlace: Transferable Circuit Global Placement via Graph Neural Networkcited by 0
  3. 2025MAGNet: A Multi-Scale Attention-Guided Graph Fusion Network for DRC Violation Detectioncited by 0
  4. 2025A Spatio-Temporal Graph Neural Networks Approach for Predicting Silent Data Corruption inducing Circuit-Level Faultscited by 0
  5. 2026VeriHGN: Heterogeneous Graph-Based Congestion Prediction for Chip Layout Verificationcited by 0
  6. 2026Graph Computation Meets Circuit Algebra: A Task-Aligned Analysis of Graph Neural Networks for Electronic Design Automationcited by 0