AppGNN: Approximation-Aware Functional Reverse Engineering using Graph Neural Networks
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Abstract (arXiv)
The globalization of the Integrated Circuit (IC) market is attracting an ever-growing number of partners, while remarkably lengthening the supply chain. Thereby, security concerns, such as those imposed by functional Reverse Engineering (RE), have become quintessential. RE leads to disclosure of confidential information to competitors, potentially enabling the theft of intellectual property. Traditional functional RE methods analyze a given gate-level netlist through employing pattern matching towards reconstructing the underlying basic blocks, and hence, reverse engineer the circuit's function. In this work, we are the first to demonstrate that applying Approximate Computing (AxC) principles to circuits significantly improves the resiliency against RE. This is attributed to the increased complexity in the underlying pattern-matching process. The resiliency remains effective even for Graph Neural Networks (GNNs) that are presently one of the most powerful state-of-the-art techniques in functional RE. Using AxC, we demonstrate a substantial reduction in GNN average classification accuracy-- from 98% to a mere 53%. To surmount the challenges introduced by AxC in RE, we propose the highly promising AppGNN platform, which enables GNNs (still being trained on exact circuits) to: (i) perform accurate classifications, and (ii) reverse engineer the circuit functionality, notwithstanding the applied approximation technique. AppGNN accomplishes this by implementing a novel graph-based node sampling approach that mimics generic approximation methodologies, requiring zero knowledge of the targeted approximation type. We perform an extensive evaluation and show that, using our method, we can improve the classification accuracy from 53% to 81% when classifying approximate adder circuits that have been generated using evolutionary algorithms, which our method is oblivious of.
Key facts. Cited by 7 papers in the map (data through 14 Oct 2026). First posted on arXiv 23 Aug 2022.
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Citing papers per year: 2022: 1; 2023: 1; 2024: 1; 2025: 2; 2026: 2.
7 papers.
- 2023Verilog-to-PyG -- A Framework for Graph Learning and Augmentation on RTL Designscited by 5
- 2022Graph Neural Networks: A Powerful and Versatile Tool for Advancing Design, Reliability, and Security of ICscited by 3
- 2025DICE: Device-level Integrated Circuits Encoder with Graph Contrastive Pretrainingcited by 2
- 2024A Benchmark on Directed Graph Representation Learning in Hardware Designscited by 1
- 2025Estimating Voltage Drop: Models, Features and Data Representation Towards a Neural Surrogatecited by 0
- 2026Wrong Code, Right Structure: Learning Netlist Representations from Imperfect LLM-Generated RTLcited by 0
- 2026ReDIL-GNN: Resynthesis Domain Incremental Learning for Circuit Graph Neural Networkscited by 0
- 2026ReDIL-GNN: Resynthesis Domain Incremental Learning for Circuit Graph Neural Networks16 Sep 2026
- 2026Wrong Code, Right Structure: Learning Netlist Representations from Imperfect LLM-Generated RTL10 Mar 2026
- 2025DICE: Device-level Integrated Circuits Encoder with Graph Contrastive Pretraining13 Feb 2025
- 2025Estimating Voltage Drop: Models, Features and Data Representation Towards a Neural Surrogate7 Feb 2025
- 2024A Benchmark on Directed Graph Representation Learning in Hardware Designs9 Oct 2024
- 2023Verilog-to-PyG -- A Framework for Graph Learning and Augmentation on RTL Designs9 Nov 2023
- 2022Graph Neural Networks: A Powerful and Versatile Tool for Advancing Design, Reliability, and Security of ICs29 Nov 2022