mlsanityData to 14 Oct 2026

SANGAM: SystemVerilog Assertion Generation via Monte Carlo Tree Self-Refine

arXiv 2506.13983 ↗First posted 11 Jun 2025cs.AIcited by 2

On the map: LLM reasoning → Reasoning for agents, planning and code

Abstract (arXiv)

Recent advancements in the field of reasoning using Large Language Models (LLMs) have created new possibilities for more complex and automatic Hardware Assertion Generation techniques. This paper introduces SANGAM, a SystemVerilog Assertion Generation framework using LLM-guided Monte Carlo Tree Search for the automatic generation of SVAs from industry-level specifications. The proposed framework utilizes a three-stage approach: Stage 1 consists of multi-modal Specification Processing using Signal Mapper, SPEC Analyzer, and Waveform Analyzer LLM Agents. Stage 2 consists of using the Monte Carlo Tree Self-Refine (MCTSr) algorithm for automatic reasoning about SVAs for each signal, and finally, Stage 3 combines the MCTSr-generated reasoning traces to generate SVA assertions for each signal. The results demonstrated that our framework, SANGAM, can generate a robust set of SVAs, performing better in the evaluation process in comparison to the recent methods.

Key facts. Cited by 2 papers in the map (data through 14 Oct 2026). Placed in Reasoning for agents, planning and code, one of 17 directions in LLM reasoning. Builds on 13 of its 21 references that are in the map. First posted on arXiv 11 Jun 2025.

Builds on

13 of 21 references.

References · 13

  1. 2025DeepSeek-R1: Incentivizing Reasoning Capability in LLMs via Reinforcement Learningcited by 6,330
  2. 2024Improve Mathematical Reasoning in Language Models by Automated Process Supervisioncited by 441
  3. 2024Accessing GPT-4 level Mathematical Olympiad Solutions via Monte Carlo Tree Self-refine with LLaMa-3 8Bcited by 158
  4. 2024Interpretable Contrastive Monte Carlo Tree Search Reasoningcited by 64
  5. 2023(Security) Assertions by Large Language Modelscited by 32
  6. 2024AssertLLM: Generating and Evaluating Hardware Verification Assertions from Design Specifications via Multi-LLMscited by 31
  7. 2024AssertLLM: Generating Hardware Verification Assertions from Design Specifications via Multi-LLMscited by 31
  8. 2024LayoutCopilot: An LLM-powered Multi-agent Collaborative Framework for Interactive Analog Layout Designcited by 25
  9. 2024HLSPilot: LLM-based High-Level Synthesiscited by 25
  10. 2024Automatically Improving LLM-based Verilog Generation using EDA Tool Feedbackcited by 19
  11. 2024ChIRAAG: ChatGPT Informed Rapid and Automated Assertion Generationcited by 16
  12. 2024VHDL-Eval: A Framework for Evaluating Large Language Models in VHDL Code Generationcited by 15
1 more
  1. 2024Large Language Model (LLM) for Standard Cell Layout Design Optimizationcited by 9

Built on by

Cited by year (2026 to 14 Oct)

Citing papers per year: 2026: 2.

2 papers.

  1. 2026SpecAlign: A Semantic Alignment Framework for SystemVerilog Assertion Generationcited by 1
  2. 2026HierSVA: A Data Synthesis Pipeline, Dataset, and Benchmark for LLM-Driven Hierarchical Hardware Formal Verificationcited by 0

Similar, not cited

Close in wording, no citation either way

  1. 2026From Language to Logic: Bridging LLMs & Formal Representations for RTL Assertion Generation
  2. 2025AssertCoder: LLM-Based Assertion Generation via Multimodal Specification Extraction
  3. 2026QiMeng-CodeV-SVA: Training Specialized LLMs for Hardware Assertion Generation via RTL-Grounded Bidirectional Data Synthesis
  4. 2025Hybrid-NL2SVA: Integrating RAG and Finetuning for LLM-based NL2SVA
  5. 2024MetRex: A Benchmark for Verilog Code Metric Reasoning Using LLMs
  6. 2026Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement
  7. 2026A Survey on LLM-Integrated Hardware Design Verification
  8. 2025SV-LLM: An Agentic Approach for SoC Security Verification using Large Language Models