LintLLM: An Open-Source Verilog Linting Framework Based on Large Language Models
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Abstract (arXiv)
Code Linting tools are vital for detecting potential defects in Verilog code. However, the limitations of traditional Linting tools are evident in frequent false positives and redundant defect reports. Recent advancements in large language models (LLM) have introduced new possibilities in this area. In this paper, we propose LintLLM, an open-source Linting framework that utilizes LLMs to detect defects in Verilog code via Prompt of Logic-Tree and Defect Tracker. Furthermore, we create an open-source benchmark using the mutation-based defect injection technique to evaluate LLM's ability in detecting Verilog defects. Experimental results show that o1-mini improves the correct rate by 18.89% and reduces the false-positive rate by 15.56% compared with the best-performing EDA tool. Simultaneously, LintLLM operates at less than one-tenth of the cost of commercial EDA tools. This study demonstrates the potential of LLM as an efficient and cost-effective Linting tool for hardware design. The benchmark and experimental results are open-source at URL: https://github.com/fangzhigang32/Static-Verilog-Analysis
Key facts. Cited by 7 papers in the map (data through 14 Oct 2026). First posted on arXiv 15 Feb 2025.
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Citing papers per year: 2025: 4; 2026: 3.
7 papers.
- 2025A Survey of Circuit Foundation Model: Foundation AI Models for VLSI Circuit Design and EDAcited by 17
- 2025MARVEL: Multi-Agent RTL Vulnerability Extraction using Large Language Modelscited by 5
- 2026TimingLLM: A Two-Stage Retrieval-Augmented Framework for Pre-Synthesis Timing Prediction from Verilogcited by 1
- 2026VeriPilot: An LLM-Powered Verilog Debugging Frameworkcited by 1
- 2025RocketPPA: Code-Level Power, Performance, and Area Prediction via LLM and Mixture of Expertscited by 0
- 2025MetaLint: Easy-to-Hard Generalization for Code Lintingcited by 0
- 2026Agentic Electronic Design Automation: A Handoff Perspectivecited by 0
- 2026VeriPilot: An LLM-Powered Verilog Debugging Framework22 Jun 2026
- 2026Agentic Electronic Design Automation: A Handoff Perspective18 Jun 2026
- 2026TimingLLM: A Two-Stage Retrieval-Augmented Framework for Pre-Synthesis Timing Prediction from Verilog26 Apr 2026
- 2025MetaLint: Easy-to-Hard Generalization for Code Linting15 Jul 2025
- 2025MARVEL: Multi-Agent RTL Vulnerability Extraction using Large Language Models17 May 2025
- 2025A Survey of Circuit Foundation Model: Foundation AI Models for VLSI Circuit Design and EDA28 Mar 2025
- 2025RocketPPA: Code-Level Power, Performance, and Area Prediction via LLM and Mixture of Experts27 Mar 2025