LLM-IFT: LLM-Powered Information Flow Tracking for Secure Hardware
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Abstract (arXiv)
As modern hardware designs grow in complexity and size, ensuring security across the confidentiality, integrity, and availability (CIA) triad becomes increasingly challenging. Information flow tracking (IFT) is a widely-used approach to tracing data propagation, identifying unauthorized activities that may compromise confidentiality or/and integrity in hardware. However, traditional IFT methods struggle with scalability and adaptability, particularly in high-density and interconnected architectures, leading to tracing bottlenecks that limit applicability in large-scale hardware. To address these limitations and show the potential of transformer-based models in integrated circuit (IC) design, this paper introduces LLM-IFT that integrates large language models (LLM) for the realization of the IFT process in hardware. LLM-IFT exploits LLM-driven structured reasoning to perform hierarchical dependency analysis, systematically breaking down even the most complex designs. Through a multi-step LLM invocation, the framework analyzes both intra-module and inter-module dependencies, enabling comprehensive IFT assessment. By focusing on a set of Trust-Hub vulnerability test cases at both the IP level and the SoC level, our experiments demonstrate a 100% success rate in accurate IFT analysis for confidentiality and integrity checks in hardware.
Key facts. Cited by 5 papers in the map (data through 14 Oct 2026). First posted on arXiv 9 Apr 2025.
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Citing papers per year: 2025: 3; 2026: 2.
5 papers.
- 2025RTL++: Graph-enhanced LLM for RTL Code Generationcited by 18
- 2025DecoRTL: A Run-time Decoding Framework for RTL Code Generation with LLMscited by 5
- 2025VerilogLAVD: LLM-Aided Rule Generation for Vulnerability Detection in Verilogcited by 2
- 2026SafeTune: Mitigating Data Poisoning in LLM Fine-Tuning for RTL Code Generationcited by 2
- 2026CASS-RTL: Correctness-Aware Subspace Steering for RTL Generation with LLMscited by 0
- 2026CASS-RTL: Correctness-Aware Subspace Steering for RTL Generation with LLMs4 Jun 2026
- 2026SafeTune: Mitigating Data Poisoning in LLM Fine-Tuning for RTL Code Generation29 Apr 2026
- 2025VerilogLAVD: LLM-Aided Rule Generation for Vulnerability Detection in Verilog18 Aug 2025
- 2025DecoRTL: A Run-time Decoding Framework for RTL Code Generation with LLMs3 Jul 2025
- 2025RTL++: Graph-enhanced LLM for RTL Code Generation11 May 2025