SparseLUT: Sparse Connectivity Optimization for Lookup Table-based Deep Neural Networks
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Abstract (arXiv)
The deployment of deep neural networks (DNNs) on resource-constrained edge devices such as field-programmable gate arrays (FPGAs) requires a careful balance of latency, power, and resource usage while maintaining high accuracy. Existing Lookup Table (LUT)-based DNNs, including LogicNets, PolyLUT, PolyLUT-Add, and NeuraLUT, exploit native FPGA resources with random sparse connectivity. This paper introduces SparseLUT, a connectivity-centric training technique tailored for LUT-based DNNs. SparseLUT leverages a non-greedy training strategy that prioritizes the pruning of less significant connections and strategically regrows alternative ones, resulting in efficient convergence to the target sparsity. Experimental results show consistent accuracy improvements across benchmarks, including up to a 2.13% increase on MNIST and a 0.94% improvement for Jet Substructure Classification compared to random sparsity. This is done without any hardware overhead and achieves state-of-the-art results for LUT-based DNNs.
Key facts. Cited by 2 papers in the map (data through 14 Oct 2026). Builds on 17 of its 27 references that are in the map. First posted on arXiv 17 Mar 2025.
Builds on
17 of 27 references.
References · 17
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- 2020LogicNets: Co-Designed Neural Networks and Circuits for Extreme-Throughput Applicationscited by 57
5 more
- 2020Compressing deep neural networks on FPGAs to binary and ternary precision with HLS4MLcited by 42
- 2023Dynamic Sparse Training with Structured Sparsitycited by 38
- 2023PolyLUT: Learning Piecewise Polynomials for Ultra-Low Latency FPGA LUT-based Inferencecited by 30
- 2024NeuraLUT: Hiding Neural Network Density in Boolean Synthesizable Functionscited by 21
- 2024PolyLUT-Add: FPGA-based LUT Inference with Wide Inputscited by 12
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Citing papers per year: 2026: 2.
2 papers.