mlsanityData to 14 Oct 2026

CovR: Coverage-Aware Hardware Verification via Reasoning-Guided Reinforcement Learning

arXiv 2609.19189 ↗First posted 15 Sep 2026cs.AR cs.CLcited by 0

On the map: LLM reasoning → Reasoning for agents, planning and code

Abstract (arXiv)

Design verification remains one of the most resource-intensive stages of hardware development, often consuming up to 70% of the total design effort. While recent work has explored using Large Language Models (LLMs) to automate testbench generation, most existing approaches focus narrowly on functional correctness, overlooking the critical aspect of coverage quality. To bridge this gap, we present CovR, an agentic framework for automated testbench generation that combines self-reflection loops with simulation-based feedback to maximize coverage. Using this pipeline, we construct a large-scale dataset of 16,514 natural specification RTL reasoning testbench tuples with a strong teacher model, enabling coverage-aware supervision. Building on this, we propose a reinforcement learning (RL) framework tailored for coverage-driven testbench generation, leveraging tool-derived rewards from simulation and coverage feedback to optimize a student model. Experimental results show that the CovR finetuned model achieves 93.81% cov@10 on VerilogEval and RTLLM V2.0, and 87.76% cov@10 on CVDP, outperforming state-of-the-art approaches by 7.97% and 3.59%, respectively. Furthermore, deploying the finetuned model back into the agentic refinement pipeline further improves cov@10 to 94.27% on VerilogEval and RTLLM V2.0 and 91.39% on CVDP. Moreover, when integrated as a plug-in stimulus engine for full verification workflows, CovR improves coverage by 18.95% and mutation detection score by 1.19%, while revealing 4.46% undetected failures, highlighting the importance of optimizing for coverage in LLM-based hardware verification.

Key facts. No citing papers in the map yet (data through 14 Oct 2026). Placed in Reasoning for agents, planning and code, one of 17 directions in LLM reasoning. Builds on 16 of its 49 references that are in the map. First posted on arXiv 15 Sep 2026.

Builds on

16 of 49 references.

Closest ancestors · 4

Same direction, newest first

  1. 2026GRPO with State Mutations: Improving LLM-Based Hardware Test Plan Generation12 Jan
  2. 2025PRO-V-R1: Reasoning Enhanced Programming Agent for RTL Verification13 Jun
  3. 2025VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generation17 May
  4. 2024Qwen2.5-Coder Technical Report18 Sep

Other references · 12

  1. 2025Qwen3 Technical Reportcited by 8,820
  2. 2021Evaluating Large Language Models Trained on Codecited by 8,320
  3. 2025DeepSeek-R1: Incentivizing Reasoning Capability in LLMs via Reinforcement Learningcited by 6,330
  4. 2025SFT Memorizes, RL Generalizes: A Comparative Study of Foundation Model Post-trainingcited by 672
  5. 2025Agentic Context Engineering: Evolving Contexts for Self-Improving Language Modelscited by 398
  6. 2025Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verificationcited by 44
  7. 2024How Efficient is LLM-Generated Code? A Rigorous & High-Standard Benchmarkcited by 43
  8. 2025VeriThoughts: Enabling Automated Verilog Code Generation using Reasoning and Formal Verificationcited by 15
  9. 2025Insights from Verification: Training a Verilog Generation LLM with Reinforcement Learning with Testbench Feedbackcited by 14
  10. 2026LLM4Cov: Execution-Aware Agentic Learning for High-coverage Testbench Generationcited by 5
  11. 2025TB or Not TB: Coverage-Driven Direct Preference Optimization for Verilog Stimulus Generationcited by 4
  12. 2026RTLSeek: Boosting the LLM-Based RTL Generation with Multi-Stage Diversity-Oriented Reinforcement Learningcited by 4

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Not cited yet.

Similar, not cited

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  1. 2026AgentDV: Closed-Loop Agentic AI for Hardware Design Verification
  2. 2026EvolveGen: Algorithmic Level Hardware Model Checking Benchmark Generation through Reinforcement Learning
  3. 2024Efficient Stimuli Generation using Reinforcement Learning in Design Verification
  4. 2026GoGoTB: Agentic RTL Verification with Specification-Grounded Coverage Closure
  5. 2026ACE-RTL: When Agentic Context Evolution Meets RTL-Specialized LLMs
  6. 2026BEHAVE: Functional Behavior Modeling Enables Self-Improving Agents for Hardware Design and Verification
  7. 2026A Survey on LLM-Integrated Hardware Design Verification
  8. 2026Agentic AI-based Coverage Closure for Formal Verification