WARP-LUTs -- Walsh-Assisted Relaxation for Probabilistic Look Up Tables
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Abstract (arXiv)
Fast and efficient machine learning is of growing interest to the scientific community and has spurred significant research into novel model architectures and hardware-aware design. Recent hard? and software co-design approaches have demonstrated impressive results with entirely multiplication-free models. Differentiable Logic Gate Networks (DLGNs), for instance, provide a gradient-based framework for learning optimal combinations of low-level logic gates, setting state-of-the-art trade-offs between accuracy, resource usage, and latency. However, these models suffer from high computational cost during training and do not generalize well to logic blocks with more inputs. In this work, we introduce Walsh-Assisted Relaxation for Probabilistic Look-Up Tables (WARP-LUTs) - a novel gradient-based method that efficiently learns combinations of logic gates with substantially fewer trainable parameters. We demonstrate that WARP-LUTs achieve significantly faster convergence on CIFAR-10 compared to DLGNs, while maintaining comparable accuracy. Furthermore, our approach suggests potential for extension to higher-input logic blocks, motivating future research on extremely efficient deployment on modern FPGAs and its real-time science applications.
Key facts. Cited by 6 papers in the map (data through 14 Oct 2026). Builds on 21 of its 32 references that are in the map. First posted on arXiv 17 Oct 2025.
Builds on
21 of 32 references.
References · 21
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- 2019DeepShift: Towards Multiplication-Less Neural Networkscited by 54
- 2021Fast convolutional neural networks on FPGAs with hls4mlcited by 42
- 2024Convolutional Differentiable Logic Gate Networkscited by 37
9 more
- 2024Differentiable Weightless Neural Networkscited by 28
- 2025TreeLUT: An Efficient Alternative to Deep Neural Networks for Inference Acceleration Using Gradient Boosted Decision Treescited by 15
- 2022Weightless Neural Networks for Efficient Edge Inferencecited by 13
- 2024Learning Interpretable Differentiable Logic Networkscited by 10
- 2024HGQ: High Granularity Quantization for Real-time Neural Networks on FPGAscited by 9
- 2023ULEEN: A Novel Architecture for Ultra Low-Energy Edge Neural Networkscited by 8
- 2025A Method for Optimizing Connections in Differentiable Logic Gate Networkscited by 5
- 2025Scalable Interconnect Learning in Boolean Networkscited by 4
- 2024BOLD: Boolean Logic Deep Learningcited by 3
Built on by
Citing papers per year: 2025: 1; 2026: 5.
6 papers.
- 2026Fully Trainable Deep Differentiable Logic Gate Networks and Lookup Table Networkscited by 2
- 2025Differentiable Weightless Controllers: Learning Logic Circuits for Continuous Controlcited by 1
- 2026Inter-patient ECG Arrhythmia Classification with LGNs and LUTNscited by 1
- 2026Differentiable Logic Synthesis: Spectral Coefficient Selection via Sinkhorn-Constrained Compositioncited by 1
- 2026BitLogic: Training Framework for Gradient-Based FPGA-Native Neural Networkscited by 1
- 2026DiffLUT-Net: Differentiable Training of FPGA LUT Networks with Learnable Connectivitycited by 0
- 2026DiffLUT-Net: Differentiable Training of FPGA LUT Networks with Learnable Connectivity8 Sep 2026
- 2026Fully Trainable Deep Differentiable Logic Gate Networks and Lookup Table Networks10 Jul 2026
- 2026BitLogic: Training Framework for Gradient-Based FPGA-Native Neural Networks7 Feb 2026
- 2026Differentiable Logic Synthesis: Spectral Coefficient Selection via Sinkhorn-Constrained Composition20 Jan 2026
- 2026Inter-patient ECG Arrhythmia Classification with LGNs and LUTNs16 Jan 2026
- 2025Differentiable Weightless Controllers: Learning Logic Circuits for Continuous Control1 Dec 2025