LUTMUL: Exceed Conventional FPGA Roofline Limit by LUT-based Efficient Multiplication for Neural Network Inference
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Abstract (arXiv)
For FPGA-based neural network accelerators, digital signal processing (DSP) blocks have traditionally been the cornerstone for handling multiplications. This paper introduces LUTMUL, which harnesses the potential of look-up tables (LUTs) for performing multiplications. The availability of LUTs typically outnumbers that of DSPs by a factor of 100, offering a significant computational advantage. By exploiting this advantage of LUTs, our method demonstrates a potential boost in the performance of FPGA-based neural network accelerators with a reconfigurable dataflow architecture. Our approach challenges the conventional peak performance on DSP-based accelerators and sets a new benchmark for efficient neural network inference on FPGAs. Experimental results demonstrate that our design achieves the best inference speed among all FPGA-based accelerators, achieving a throughput of 1627 images per second and maintaining a top-1 accuracy of 70.95% on the ImageNet dataset.
Key facts. Cited by 2 papers in the map (data through 14 Oct 2026). Builds on 15 of its 37 references that are in the map. First posted on arXiv 1 Nov 2024.
Builds on
15 of 37 references.
References · 15
- 2018MobileNetV2: Inverted Residuals and Linear Bottleneckscited by 4,795
- 2016FINN: A Framework for Fast, Scalable Binarized Neural Network Inferencecited by 150
- 2019AdaBits: Neural Network Quantization with Adaptive Bit-Widthscited by 64
- 2024FlightLLM: Efficient Large Language Model Inference with a Complete Mapping Flow on FPGAscited by 64
- 2020LogicNets: Co-Designed Neural Networks and Circuits for Extreme-Throughput Applicationscited by 57
- 2018FINN-R: An End-to-End Deep-Learning Framework for Fast Exploration of Quantized Neural Networkscited by 56
- 2020FracBits: Mixed Precision Quantization via Fractional Bit-Widthscited by 55
- 2020FTRANS: Energy-Efficient Acceleration of Transformers using FPGAcited by 54
- 2023Understanding the Potential of FPGA-Based Spatial Acceleration for Large Language Model Inferencecited by 33
- 2023PolyLUT: Learning Piecewise Polynomials for Ultra-Low Latency FPGA LUT-based Inferencecited by 30
- 2022Auto-ViT-Acc: An FPGA-Aware Automatic Acceleration Framework for Vision Transformer with Mixed-Scheme Quantizationcited by 29
- 2019LUTNet: Rethinking Inference in FPGA Soft Logiccited by 28
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Citing papers per year: 2026: 2.
2 papers.
- 2026Continuous-Flow Data-Rate-Aware CNN Inference on FPGAcited by 1
- 2026Data-Rate-Aware High-Speed CNN Inference on FPGAscited by 0
- 2026Data-Rate-Aware High-Speed CNN Inference on FPGAs18 Feb 2026
- 2026Continuous-Flow Data-Rate-Aware CNN Inference on FPGA16 Jan 2026