mlsanityData to 7 Oct 2026

ARCS: Autoregressive Circuit Synthesis with Topology-Aware Graph Attention and Spec Conditioning

arXiv 2603.29068 ↗First posted 30 Mar 2026cs.LG cs.ARcited by 0

Not on the map. Why?

Abstract (arXiv)

This paper presents ARCS (Autoregressive Circuit Synthesis), a system for amortized analog circuit generation. ARCS produces complete, SPICE-simulatable designs (topology and component values) in milliseconds rather than the minutes required by search-based methods. A hybrid pipeline combines two learned generators, a graph VAE and a flow-matching model, with SPICE-based ranking. It achieves 99.9% simulation validity (reward 6.43/8.0) across 32 topologies using only 8 SPICE evaluations, 40x fewer than genetic algorithms. For single-model inference, a topology-aware Graph Transformer with Best-of-3 candidate selection reaches 85% simulation validity in 97ms, over 600x faster than random search. The key technical contribution adapts Group Relative Policy Optimization (GRPO) to multi-topology circuit reinforcement learning. GRPO resolves a critical failure mode of REINFORCE, cross-topology reward distribution mismatch, through per-topology advantage normalization. This improves simulation validity by +9.6 percentage points over REINFORCE in only 500 RL steps (10x fewer). Grammar-constrained decoding additionally guarantees 100% structural validity by construction via topology-aware token masking.

Key facts. No citing papers in the map yet (data through 7 Oct 2026). Builds on 20 of its 32 references that are in the map. First posted on arXiv 30 Mar 2026.

Builds on

20 of 32 references.

References · 20

  1. 2021Training Verifiers to Solve Math Word Problemscited by 9,743
  2. 2024DeepSeekMath: Pushing the Limits of Mathematical Reasoning in Open Language Modelscited by 8,851
  3. 2022Scalable Diffusion Models with Transformerscited by 5,931
  4. 2022Flow Matching for Generative Modelingcited by 5,426
  5. 2024Scaling LLM Test-Time Compute Optimally can be More Effective than Scaling Model Parameterscited by 1,928
  6. 2020GLU Variants Improve Transformercited by 1,724
  7. 2019Root Mean Square Layer Normalizationcited by 1,425
  8. 2022DiGress: Discrete Denoising diffusion for graph generationcited by 503
  9. 2017Lexically Constrained Decoding for Sequence Generation Using Grid Beam Searchcited by 234
  10. 2020GCN-RL Circuit Designer: Transferable Transistor Sizing with Graph Neural Networks and Reinforcement Learningcited by 89
  11. 2023EigenFold: Generative Protein Structure Prediction with Diffusion Modelscited by 63
  12. 2023CktGNN: Circuit Graph Neural Network for Electronic Design Automationcited by 55
8 more
  1. 2020AutoCkt: Deep Reinforcement Learning of Analog Circuit Designscited by 51
  2. 2024LaMAGIC: Language-Model-based Topology Generation for Analog Integrated Circuitscited by 32
  3. 2024AnalogXpert: Automating Analog Topology Synthesis by Incorporating Circuit Design Expertise into Large Language Modelscited by 17
  4. 2025AUTOCIRCUIT-RL: Reinforcement Learning-Driven LLM for Automated Circuit Topology Generationcited by 10
  5. 2024INSIGHT: Universal Neural Simulator for Analog Circuits Harnessing Autoregressive Transformerscited by 8
  6. 2024CIRCUITSYNTH: Leveraging Large Language Models for Circuit Topology Synthesiscited by 5
  7. 2025FALCON: An ML Framework for Fully Automated Layout-Constrained Analog Circuit Designcited by 4
  8. 2026AstRL: Analog and Mixed-Signal Circuit Synthesis with Deep Reinforcement Learningcited by 1

Built on by

Not cited yet.

Similar, not cited

Close in wording, no citation either way

  1. 2026EXPLORE: Exploration with Guided Search for Analog Topology Generation using Language Models
  2. 2025AnalogSAGE: Self-evolving Analog Design Multi-Agents with Stratified Memory and Grounded Experience
  3. 2024CktGen: Automated Analog Circuit Design with Generative Artificial Intelligence
  4. 2025AnalogCoder-Pro: Unifying Analog Circuit Generation and Optimization via Multi-modal LLMs
  5. 2025TopoSizing: An LLM-aided Framework of Topology-based Understanding and Sizing for AMS Circuits
  6. 2026AaLLM: An End-to-End Analog Circuit Design Framework from Topology Generation to Sizing Using Large Language Models
  7. 2024M3: Mamba-assisted Multi-Circuit Optimization via MBRL with Effective Scheduling
  8. 2026Simulation-Aware In-Context Policy Improvement for LLM-Aided Analog Layout Refinement