ALIGN: A System for Automating Analog Layout
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Abstract (arXiv)
ALIGN ("Analog Layout, Intelligently Generated from Netlists") is an open-source automatic layout generation flow for analog circuits. ALIGN translates an input SPICE netlist to an output GDSII layout, specific to a given technology, as specified by a set of design rules. The flow first automatically detects hierarchies in the circuit netlist and translates layout synthesis to a problem of hierarchical block assembly. At the lowest level, parameterized cells are generated using an abstraction of the design rules; these blocks are then assembled under geometric and electrical constraints to build the circuit layout. ALIGN has been applied to generate layouts for a diverse set of analog circuit families: low frequency analog blocks, wireline circuits, wireless circuits, and power delivery circuits.
Key facts. Cited by 8 papers in the map (data through 7 Oct 2026). First posted on arXiv 24 Aug 2020.
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Citing papers per year: 2024: 1; 2025: 5; 2026: 2.
8 papers.
- 2024Effective Analog ICs Floorplanning with Relational Graph Neural Networks and Reinforcement Learningcited by 5
- 2025FALCON: An ML Framework for Fully Automated Layout-Constrained Analog Circuit Designcited by 4
- 2025ZeroSim: Zero-Shot Analog Circuit Evaluation with Unified Transformer Embeddingscited by 2
- 2026OSIRIS: Bridging Analog Circuit Design and Machine Learning with Scalable Dataset Generationcited by 2
- 2025Emerging ML-AI Techniques for Analog and RF EDAcited by 1
- 2026NetlistBench: Evaluating LLM Reliability in SPICE Netlist Recognition and Manipulationcited by 1
- 2025Advancing Routing-Awareness in Analog ICs Floorplanningcited by 0
- 2025LLMs for Analog Circuit Design Continuum (ACDC)cited by 0
- 2026NetlistBench: Evaluating LLM Reliability in SPICE Netlist Recognition and Manipulation12 Aug 2026
- 2026OSIRIS: Bridging Analog Circuit Design and Machine Learning with Scalable Dataset Generation27 Jan 2026
- 2025LLMs for Analog Circuit Design Continuum (ACDC)9 Dec 2025
- 2025ZeroSim: Zero-Shot Analog Circuit Evaluation with Unified Transformer Embeddings10 Nov 2025
- 2025Advancing Routing-Awareness in Analog ICs Floorplanning17 Oct 2025
- 2025FALCON: An ML Framework for Fully Automated Layout-Constrained Analog Circuit Design28 May 2025
- 2025Emerging ML-AI Techniques for Analog and RF EDA12 May 2025
- 2024Effective Analog ICs Floorplanning with Relational Graph Neural Networks and Reinforcement Learning20 Nov 2024