mlsanityData to 14 Oct 2026

GraCo -- A Graph Composer for Integrated Circuits

arXiv 2411.13890 ↗First posted 21 Nov 2024cs.LG cs.ARcited by 2

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Abstract (arXiv)

Designing integrated circuits involves substantial complexity, posing challenges in revealing its potential applications - from custom digital cells to analog circuits. Despite extensive research over the past decades in building versatile and automated frameworks, there remains open room to explore more computationally efficient AI-based solutions. This paper introduces the graph composer GraCo, a novel method for synthesizing integrated circuits using reinforcement learning (RL). GraCo learns to construct a graph step-by-step, which is then converted into a netlist and simulated with SPICE. We demonstrate that GraCo is highly configurable, enabling the incorporation of prior design knowledge into the framework. We formalize how this prior knowledge can be utilized and, in particular, show that applying consistency checks enhances the efficiency of the sampling process. To evaluate its performance, we compare GraCo to a random baseline, which is known to perform well for smaller design space problems. We demonstrate that GraCo can discover circuits for tasks such as generating standard cells, including the inverter and the two-input NAND (NAND2) gate. Compared to a random baseline, GraCo requires 5x fewer sampling steps to design an inverter and successfully synthesizes a NAND2 gate that is 2.5x faster.

Key facts. Cited by 2 papers in the map (data through 14 Oct 2026). Builds on 9 of its 33 references that are in the map. First posted on arXiv 21 Nov 2024.

Builds on

9 of 33 references.

References · 9

  1. 2017Evolution Strategies as a Scalable Alternative to Reinforcement Learningcited by 574
  2. 2019DeepGCNs: Can GCNs Go as Deep as CNNs?cited by 527
  3. 2016Safe and Efficient Off-Policy Reinforcement Learningcited by 264
  4. 2020DeeperGCN: All You Need to Train Deeper GCNscited by 250
  5. 2018Top-K Off-Policy Correction for a REINFORCE Recommender Systemcited by 182
  6. 2023CktGNN: Circuit Graph Neural Network for Electronic Design Automationcited by 58
  7. 2020AutoCkt: Deep Reinforcement Learning of Analog Circuit Designscited by 51
  8. 2021DNN-Opt: An RL Inspired Optimization for Analog Circuit Sizing using Deep Neural Networkscited by 18
  9. 2022Pretraining Graph Neural Networks for few-shot Analog Circuit Modeling and Designcited by 13

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Cited by year (2026 to 14 Oct)

Citing papers per year: 2025: 1; 2026: 1.

2 papers.

  1. 2025SPICEMixer - Netlist-Level Circuit Evolutioncited by 1
  2. 2026Spicing up Genetic Netlist Generation with LLMscited by 0

Similar, not cited

Close in wording, no citation either way

  1. 2026AstRL: Analog and Mixed-Signal Circuit Synthesis with Deep Reinforcement Learning
  2. 2026ARCS: Autoregressive Circuit Synthesis with Topology-Aware Graph Attention and Spec Conditioning
  3. 2025AUTOCIRCUIT-RL: Reinforcement Learning-Driven LLM for Automated Circuit Topology Generation
  4. 2024ShortCircuit: AlphaZero-Driven Circuit Design
  5. 2023INVICTUS: Optimizing Boolean Logic Circuit Synthesis via Synergistic Learning and Search
  6. 2024Retrieval-Guided Reinforcement Learning for Boolean Circuit Minimization
  7. 2025CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design
  8. 2024CircuitVAE: Efficient and Scalable Latent Circuit Optimization