SINA: A Circuit Schematic Image-to-Netlist Generator Using Artificial Intelligence
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Abstract (arXiv)
Current methods for converting circuit schematic images into machine-readable netlists struggle with component recognition and connectivity inference. In this paper, we present SINA, an open-source, fully automated circuit schematic image-to-netlist generator. SINA integrates deep learning for accurate component detection, Connected-Component Labeling (CCL) for precise connectivity extraction, and Optical Character Recognition (OCR) for component reference designator retrieval, while employing a Vision-Language Model (VLM) for reliable reference designator assignments. In our experiments, SINA achieves 96.47% overall netlist-generation accuracy, which is 2.72x higher than state-of-the-art approaches.
Key facts. Cited by 4 papers in the map (data through 13 Oct 2026). Builds on 7 of its 16 references that are in the map. First posted on arXiv 29 Jan 2026.
Builds on
7 of 16 references.
References · 7
- 2023GPT-4 Technical Reportcited by 18,278
- 2015You Only Look Once: Unified, Real-Time Object Detectioncited by 4,840
- 2023VeriGen: A Large Language Model for Verilog Code Generationcited by 200
- 2024Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AIcited by 18
- 2024Schemato -- An LLM for Netlist-to-Schematic Conversioncited by 11
- 2025MuaLLM: A Multimodal Large Language Model Agent for Circuit Design Assistance with Hybrid Contextual Retrieval-Augmented Generationcited by 8
- 2021Tablext: A Combined Neural Network And Heuristic Based Table Extractorcited by 3
Built on by
Citing papers per year: 2026: 4.
4 papers.
- 2026OmniSch: A Multimodal PCB Schematic Benchmark For Structured Diagram Visual Reasoningcited by 2
- 2026ORACLE: A Multi-Objective Reinforcement Learning-Based Analog Circuit Design Optimizer with Large Language Models-Guided Explorationcited by 1
- 2026SINA: A Fully Automated Circuit Schematic Image to Netlist Generator Using Artificial Intelligencecited by 0
- 2026AaLLM: An End-to-End Analog Circuit Design Framework from Topology Generation to Sizing Using Large Language Modelscited by 0
- 2026AaLLM: An End-to-End Analog Circuit Design Framework from Topology Generation to Sizing Using Large Language Models13 Aug 2026
- 2026ORACLE: A Multi-Objective Reinforcement Learning-Based Analog Circuit Design Optimizer with Large Language Models-Guided Exploration5 Aug 2026
- 2026SINA: A Fully Automated Circuit Schematic Image to Netlist Generator Using Artificial Intelligence2 Jul 2026
- 2026OmniSch: A Multimodal PCB Schematic Benchmark For Structured Diagram Visual Reasoning31 Mar 2026
Similar, not cited
Close in wording, no citation either way
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- 2024DocEDA: Automated Extraction and Design of Analog Circuits from Documents with Large Language Model
- 2026CircuitFormer: A Circuit Language Model for Analog Topology Design from Natural Language Prompt
- 2025Graph Neural Networks Based Analog Circuit Link Prediction
- 2025AMSnet 2.0: A Large AMS Database with AI Segmentation for Net Detection
- 2025CircuitSense: A Hierarchical MLLM Benchmark Bridging Visual Comprehension and Symbolic Reasoning in Engineering Design Process
- 2026AutoVSR: Automatic Visual-to-Symbolic Reasoning for Symbolic Expression Generation from Circuit Schematic