mlsanityData to 7 Oct 2026

A flexible and fast PyTorch toolkit for simulating training and inference on analog crossbar arrays

arXiv 2104.02184 ↗First posted 5 Apr 2021cs.LG cs.ARcited by 38

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Abstract (arXiv)

We introduce the IBM Analog Hardware Acceleration Kit, a new and first of a kind open source toolkit to simulate analog crossbar arrays in a convenient fashion from within PyTorch (freely available at https://github.com/IBM/aihwkit). The toolkit is under active development and is centered around the concept of an "analog tile" which captures the computations performed on a crossbar array. Analog tiles are building blocks that can be used to extend existing network modules with analog components and compose arbitrary artificial neural networks (ANNs) using the flexibility of the PyTorch framework. Analog tiles can be conveniently configured to emulate a plethora of different analog hardware characteristics and their non-idealities, such as device-to-device and cycle-to-cycle variations, resistive device response curves, and weight and output noise. Additionally, the toolkit makes it possible to design custom unit cell configurations and to use advanced analog optimization algorithms such as Tiki-Taka. Moreover, the backward and update behavior can be set to "ideal" to enable hardware-aware training features for chips that target inference acceleration only. To evaluate the inference accuracy of such chips over time, we provide statistical programming noise and drift models calibrated on phase-change memory hardware. Our new toolkit is fully GPU accelerated and can be used to conveniently estimate the impact of material properties and non-idealities of future analog technology on the accuracy for arbitrary ANNs.

Key facts. Cited by 38 papers in the map (data through 7 Oct 2026). Builds on 5 of its 14 references that are in the map. First posted on arXiv 5 Apr 2021.

Builds on

5 of 14 references.

References · 5

  1. 2019PyTorch: An Imperative Style, High-Performance Deep Learning Librarycited by 20,160
  2. 2020DNN+NeuroSim V2.0: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators for On-chip Trainingcited by 32
  3. 2016Acceleration of Deep Neural Network Training with Resistive Cross-Point Devicescited by 28
  4. 2019Algorithm for Training Neural Networks on Resistive Device Arrayscited by 18
  5. 2018RxNN: A Framework for Evaluating Deep Neural Networks on Resistive Crossbarscited by 17

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Cited by year (2026 to 7 Oct)

Citing papers per year: 2021: 1; 2022: 4; 2023: 6; 2024: 9; 2025: 12; 2026: 6.

38 papers.

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  1. 2021Deep physical neural networks enabled by a backpropagation algorithm for arbitrary physical systemscited by 125
  2. 2023Hardware-aware training for large-scale and diverse deep learning inference workloads using in-memory computing-based acceleratorscited by 42
  3. 2023Fast offset corrected in-memory trainingcited by 11
  4. 2023AnalogNAS: A Neural Network Design Framework for Accurate Inference with Analog In-Memory Computingcited by 10
  5. 2023Using the IBM Analog In-Memory Hardware Acceleration Kit for Neural Network Training and Inferencecited by 10
  6. 2024Towards Exact Gradient-based Training on Analog In-memory Computingcited by 6
  7. 2023Examining the Role and Limits of Batchnorm Optimization to Mitigate Diverse Hardware-noise in In-memory Computingcited by 5
  8. 2025Analog In-memory Training on General Non-ideal Resistive Elements: The Impact of Response Functionscited by 4
  9. 2022Gradient-based Neuromorphic Learning on Dynamical RRAM Arrayscited by 2
  10. 2022AnalogVNN: A fully modular framework for modeling and optimizing photonic neural networkscited by 2
  11. 2025NeuroSim V1.5: Improved Software Backbone for Benchmarking Compute-in-Memory Accelerators with Device and Circuit-level Non-idealitiescited by 2
  12. 2025In-memory Training on Analog Devices with Limited Conductance States via Multi-tile Residual Learningcited by 2
26 more
  1. 2022Design Space Exploration of Dense and Sparse Mapping Schemes for RRAM Architecturescited by 1
  2. 2023A Cryogenic Memristive Neural Decoder for Fault-tolerant Quantum Error Correctioncited by 1
  3. 2024When In-memory Computing Meets Spiking Neural Networks -- A Perspective on Device-Circuit-System-and-Algorithm Co-designcited by 1
  4. 2024Efficient transformer adaptation for analog in-memory computing via low-rank adapterscited by 1
  5. 2025Regularization-based Framework for Quantization-, Fault- and Variability-Aware Trainingcited by 1
  6. 2025Optimizing Binary and Ternary Neural Network Inference on RRAM Crossbars using CIM-Explorercited by 1
  7. 2025Running Conventional Automatic Speech Recognition on Memristor Hardware: A Simulated Approachcited by 1
  8. 2025Rapid yet accurate Tile-circuit and device modeling for Analog In-Memory Computingcited by 1
  9. 2025Memristor-Based Neural Network Accelerators for Space Applications: Enhancing Performance with Temporal Averaging and SIRENscited by 1
  10. 2025Circuit realization and hardware linearization of monotone operator equilibrium networkscited by 1
  11. 2025Energy-convergence trade off for the training of neural networks on bio-inspired hardwarecited by 1
  12. 2026XBTorch: A Unified Framework for Modeling and Co-Design of Crossbar-Based Deep Learning Acceleratorscited by 1
  13. 2026Dynamic Symmetric Point Tracking: Tackling Non-ideal Reference in Analog In-memory Trainingcited by 1
  14. 2022SAMSON: Sharpness-Aware Minimization Scaled by Outlier Normalization for Improving DNN Generalization and Robustnesscited by 0
  15. 2024Analog In-Memory Computing with Uncertainty Quantification for Efficient Edge-based Medical Imaging Segmentationcited by 0
  16. 2024Comparative Evaluation of Memory Technologies for Synaptic Crossbar Arrays- Part 2: Design Knobs and DNN Accuracy Trendscited by 0
  17. 2024A Realistic Simulation Framework for Analog/Digital Neuromorphic Architecturescited by 0
  18. 2024Retro-li: Small-Scale Retrieval Augmented Generation Supporting Noisy Similarity Searches and Domain Shift Generalizationcited by 0
  19. 2024On the Convergence Theory of Pipeline Gradient-based Analog In-memory Trainingcited by 0
  20. 2024Kernel Approximation using Analog In-Memory Computingcited by 0
  21. 2025Bruno: Backpropagation Running Undersampled for Novel device Optimizationcited by 0
  22. 2025Guidance and Control Neural Network Acceleration using Memristorscited by 0
  23. 2026Joint Hardware-Workload Co-Optimization for In-Memory Computing Acceleratorscited by 0
  24. 2026A Controlled Diagnostic Study of Hardware-Induced Distortions in Hardware-Aware Trainingcited by 0
  25. 2026Leveraging ECRAM for Edge Continual Learningcited by 0
  26. 2026Making Analog Training Scale: Co-Designing Mapping, Optimizer, and Converterscited by 0

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  1. 2019Towards Efficient Neural Networks On-a-chip: Joint Hardware-Algorithm Approaches ↗
  2. 2024INSIGHT: Universal Neural Simulator for Analog Circuits Harnessing Autoregressive Transformers
  3. 2024AnalogCoder: Analog Circuit Design via Training-Free Code Generation
  4. 2025Analog Foundation Models
  5. 2025All-in-One Analog AI Hardware: On-Chip Training and Inference with Conductive-Metal-Oxide/HfOx ReRAM Devices
  6. 2025Dense Associative Memories with Analog Circuits
  7. 2026ARCS: Autoregressive Circuit Synthesis with Topology-Aware Graph Attention and Spec Conditioning
  8. 2024M3: Mamba-assisted Multi-Circuit Optimization via MBRL with Effective Scheduling