mlsanityData to 7 Oct 2026

DNN+NeuroSim V2.0: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators for On-chip Training

arXiv 2003.06471 ↗First posted 13 Mar 2020cs.ET cs.LGcited by 32

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Abstract (arXiv)

DNN+NeuroSim is an integrated framework to benchmark compute-in-memory (CIM) accelerators for deep neural networks, with hierarchical design options from device-level, to circuit-level and up to algorithm-level. A python wrapper is developed to interface NeuroSim with a popular machine learning platform: Pytorch, to support flexible network structures. The framework provides automatic algorithm-to-hardware mapping, and evaluates chip-level area, energy efficiency and throughput for training or inference, as well as training/inference accuracy with hardware constraints. Our prior work (DNN+NeuroSim V1.1) was developed to estimate the impact of reliability in synaptic devices, and analog-to-digital converter (ADC) quantization loss on the accuracy and hardware performance of inference engines. In this work, we further investigated the impact of the analog emerging non-volatile memory non-ideal device properties for on-chip training. By introducing the nonlinearity, asymmetry, device-to-device and cycle-to-cycle variation of weight update into the python wrapper, and peripheral circuits for error/weight gradient computation in NeuroSim core, we benchmarked CIM accelerators based on state-of-the-art SRAM and eNVM devices for VGG-8 on CIFAR-10 dataset, revealing the crucial specs of synaptic devices for on-chip training. The proposed DNN+NeuroSim V2.0 framework is available on GitHub.

Key facts. Cited by 32 papers in the map (data through 7 Oct 2026). First posted on arXiv 13 Mar 2020.

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Citing papers per year: 2021: 3; 2022: 1; 2023: 3; 2024: 8; 2025: 12; 2026: 5.

32 papers.

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  1. 2021A flexible and fast PyTorch toolkit for simulating training and inference on analog crossbar arrayscited by 38
  2. 2021Bottom-up and top-down approaches for the design of neuromorphic processing systems: Tradeoffs and synergies between natural and artificial intelligencecited by 21
  3. 2023Using the IBM Analog In-Memory Hardware Acceleration Kit for Neural Network Training and Inferencecited by 10
  4. 2023Examining the Role and Limits of Batchnorm Optimization to Mitigate Diverse Hardware-noise in In-memory Computingcited by 5
  5. 2024LLS: Local Learning Rule for Deep Neural Networks Inspired by Neural Activity Synchronizationcited by 5
  6. 2024ClipFormer: Key-Value Clipping of Transformers on Memristive Crossbars for Write Noise Mitigationcited by 4
  7. 2025Binary Weight Multi-Bit Activation Quantization for Compute-in-Memory CNN Acceleratorscited by 3
  8. 2024FARe: Fault-Aware GNN Training on ReRAM-based PIM Acceleratorscited by 2
  9. 2024H3DFact: Heterogeneous 3D Integrated CIM for Factorization with Holographic Perceptual Representationscited by 2
  10. 2024TReX- Reusing Vision Transformer's Attention for Efficient Xbar-based Computingcited by 2
  11. 2024Towards Efficient IMC Accelerator Design Through Joint Hardware-Workload Co-optimizationcited by 2
  12. 2025Atleus: Accelerating Transformers on the Edge Enabled by 3D Heterogeneous Manycore Architecturescited by 2
20 more
  1. 2025Low-Rank Compression for IMC Arrayscited by 2
  2. 2025NeuroSim V1.5: Improved Software Backbone for Benchmarking Compute-in-Memory Accelerators with Device and Circuit-level Non-idealitiescited by 2
  3. 2025CHIME: Chiplet-based Heterogeneous Near-Memory Acceleration for Edge Multimodal LLM Inferencecited by 2
  4. 2022Design Space Exploration of Dense and Sparse Mapping Schemes for RRAM Architecturescited by 1
  5. 2024HeTraX: Energy Efficient 3D Heterogeneous Manycore Architecture for Transformer Accelerationcited by 1
  6. 2025MEMHD: Memory-Efficient Multi-Centroid Hyperdimensional Computing for Fully-Utilized In-Memory Computing Architecturescited by 1
  7. 2025Regularization-based Framework for Quantization-, Fault- and Variability-Aware Trainingcited by 1
  8. 2025Rapid yet accurate Tile-circuit and device modeling for Analog In-Memory Computingcited by 1
  9. 2025CIMNAS: A Joint Framework for Compute-In-Memory-Aware Neural Architecture Searchcited by 1
  10. 2021SEMULATOR: Emulating the Dynamics of Crossbar Array-based Analog Neural System with Regression Neural Networkscited by 0
  11. 2023Towards Efficient Hyperdimensional Computing Using Photonicscited by 0
  12. 2024Mem-elements based Neuromorphic Hardware for Neural Network Applicationcited by 0
  13. 2025Low-power Spike-based Wearable Analytics on RRAM Crossbarscited by 0
  14. 2025Row-Column Hybrid Grouping for Fault-Resilient Multi-Bit Weight Representation on IMC Arrayscited by 0
  15. 2025HePGA: A Heterogeneous Processing-in-Memory based GNN Training Acceleratorcited by 0
  16. 2026Joint Hardware-Workload Co-Optimization for In-Memory Computing Acceleratorscited by 0
  17. 2026ThAME: 3D Memory-Enabled Heterogeneous Accelerator for LLM Mixture of Expertscited by 0
  18. 2026ThRIve: Thermally Robust CNN Inference via Low-Rank Adaptation in Heterogeneous PIM Architecturescited by 0
  19. 2026LLM Inference on IMC-NoC Architecture with Balanced Dataflow and Fine-Grained Parallelismcited by 0
  20. 2026Making Analog Training Scale: Co-Designing Mapping, Optimizer, and Converterscited by 0