Analog In-memory Training on General Non-ideal Resistive Elements: The Impact of Response Functions
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Abstract (arXiv)
As the economic and environmental costs of training and deploying large vision or language models increase dramatically, analog in-memory computing (AIMC) emerges as a promising energy-efficient solution. However, the training perspective, especially its training dynamic, is underexplored. In AIMC hardware, the trainable weights are represented by the conductance of resistive elements and updated using consecutive electrical pulses. While the conductance changes by a constant in response to each pulse, in reality, the change is scaled by asymmetric and non-linear response functions, leading to a non-ideal training dynamic. This paper provides a theoretical foundation for gradient-based training on AIMC hardware with non-ideal response functions. We demonstrate that asymmetric response functions negatively impact Analog SGD by imposing an implicit penalty on the objective. To overcome the issue, we propose Residual Learning algorithm, which provably converges exactly to a critical point by solving a bilevel optimization problem. We demonstrate that the proposed method can be extended to address other hardware imperfections, such as limited response granularity. As we know, it is the first paper to investigate the impact of a class of generic non-ideal response functions. The conclusion is supported by simulations validating our theoretical insights.
Key facts. Cited by 5 papers in the map (data through 14 Oct 2026). Builds on 25 of its 85 references that are in the map. First posted on arXiv 10 Feb 2025.
Builds on
25 of 85 references.
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13 more
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Built on by
Citing papers per year: 2025: 2; 2026: 3.
5 papers.
- 2025In-memory Training on Analog Devices with Limited Conductance States via Multi-tile Residual Learningcited by 3
- 2026Dynamic Symmetric Point Tracking: Tackling Non-ideal Reference in Analog In-memory Trainingcited by 2
- 2025Circuit realization and hardware linearization of monotone operator equilibrium networkscited by 1
- 2026Making Analog Training Scale: Co-Designing Mapping, Optimizer, and Converterscited by 1
- 2026Robust Parameter-Efficient LLM Adaptation on Analog Hardwarecited by 0
- 2026Robust Parameter-Efficient LLM Adaptation on Analog Hardware4 Oct 2026
- 2026Making Analog Training Scale: Co-Designing Mapping, Optimizer, and Converters29 Sep 2026
- 2026Dynamic Symmetric Point Tracking: Tackling Non-ideal Reference in Analog In-memory Training24 Feb 2026
- 2025In-memory Training on Analog Devices with Limited Conductance States via Multi-tile Residual Learning2 Oct 2025
- 2025Circuit realization and hardware linearization of monotone operator equilibrium networks17 Sep 2025