mlsanityData to 7 Oct 2026

When In-memory Computing Meets Spiking Neural Networks -- A Perspective on Device-Circuit-System-and-Algorithm Co-design

arXiv 2408.12767 ↗First posted 22 Aug 2024cs.NE cs.AI cs.ARcited by 1

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Abstract (arXiv)

This review explores the intersection of bio-plausible artificial intelligence in the form of Spiking Neural Networks (SNNs) with the analog In-Memory Computing (IMC) domain, highlighting their collective potential for low-power edge computing environments. Through detailed investigation at the device, circuit, and system levels, we highlight the pivotal synergies between SNNs and IMC architectures. Additionally, we emphasize the critical need for comprehensive system-level analyses, considering the inter-dependencies between algorithms, devices, circuit & system parameters, crucial for optimal performance. An in-depth analysis leads to identification of key system-level bottlenecks arising from device limitations which can be addressed using SNN-specific algorithm-hardware co-design techniques. This review underscores the imperative for holistic device to system design space co-exploration, highlighting the critical aspects of hardware and algorithm research endeavors for low-power neuromorphic solutions.

Key facts. Cited by 1 paper in the map (data through 7 Oct 2026). Builds on 46 of its 170 references that are in the map. First posted on arXiv 22 Aug 2024.

Builds on

46 of 170 references.

References · 46

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34 more
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Citing papers per year: 2025: 1.

1 paper.

  1. 2025Low-power Spike-based Wearable Analytics on RRAM Crossbarscited by 0