End-to-end codesign of Hessian-aware quantized neural networks for FPGAs and ASICs
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Abstract (arXiv)
We develop an end-to-end workflow for the training and implementation of co-designed neural networks (NNs) for efficient field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) hardware. Our approach leverages Hessian-aware quantization (HAWQ) of NNs, the Quantized Open Neural Network Exchange (QONNX) intermediate representation, and the hls4ml tool flow for transpiling NNs into FPGA and ASIC firmware. This makes efficient NN implementations in hardware accessible to nonexperts, in a single open-sourced workflow that can be deployed for real-time machine learning applications in a wide range of scientific and industrial settings. We demonstrate the workflow in a particle physics application involving trigger decisions that must operate at the 40 MHz collision rate of the CERN Large Hadron Collider (LHC). Given the high collision rate, all data processing must be implemented on custom ASIC and FPGA hardware within a strict area and latency. Based on these constraints, we implement an optimized mixed-precision NN classifier for high-momentum particle jets in simulated LHC proton-proton collisions.
Key facts. Cited by 2 papers in the map (data through 14 Oct 2026). Builds on 30 of its 49 references that are in the map. First posted on arXiv 13 Apr 2023.
Builds on
30 of 49 references.
References · 30
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18 more
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Citing papers per year: 2024: 1; 2025: 1.
2 papers.
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- 2025Hardware-Aware Neural Network Compilation with Learned Optimization: A RISC-V Accelerator Approach
- 2025Quantization Effects of Artificial Neural Networks for Embedded Edge-Computing Applications
- 2023Quantized Neural Networks for Low-Precision Accumulation with Guaranteed Overflow Avoidance
- 2025Neural Architecture Codesign for Fast Physics Applications
- 2021Automated Backend-Aware Post-Training Quantization