mlsanityData to 7 Oct 2026

ATHEENA: A Toolflow for Hardware Early-Exit Network Automation

arXiv 2304.08400 ↗First posted 17 Apr 2023cs.AR cs.LGcited by 3

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Abstract (arXiv)

The continued need for improvements in accuracy, throughput, and efficiency of Deep Neural Networks has resulted in a multitude of methods that make the most of custom architectures on FPGAs. These include the creation of hand-crafted networks and the use of quantization and pruning to reduce extraneous network parameters. However, with the potential of static solutions already well exploited, we propose to shift the focus to using the varying difficulty of individual data samples to further improve efficiency and reduce average compute for classification. Input-dependent computation allows for the network to make runtime decisions to finish a task early if the result meets a confidence threshold. Early-Exit network architectures have become an increasingly popular way to implement such behaviour in software. We create: A Toolflow for Hardware Early-Exit Network Automation (ATHEENA), an automated FPGA toolflow that leverages the probability of samples exiting early from such networks to scale the resources allocated to different sections of the network. The toolflow uses the data-flow model of fpgaConvNet, extended to support Early-Exit networks as well as Design Space Exploration to optimize the generated streaming architecture hardware with the goal of increasing throughput/reducing area while maintaining accuracy. Experimental results on three different networks demonstrate a throughput increase of 2.00× to 2.78× compared to an optimized baseline network implementation with no early exits. Additionally, the toolflow can achieve a throughput matching the same baseline with as low as 46% of the resources the baseline requires.

Key facts. Cited by 3 papers in the map (data through 7 Oct 2026). Builds on 23 of its 52 references that are in the map. First posted on arXiv 17 Apr 2023.

Builds on

23 of 52 references.

References · 23

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11 more
  1. 2020Compressing deep neural networks on FPGAs to binary and ternary precision with HLS4MLcited by 42
  2. 2020Learning to Stop While Learning to Predictcited by 30
  3. 2018Toolflows for Mapping Convolutional Neural Networks on FPGAs: A Survey and Future Directionscited by 27
  4. 2021Multi-Exit Semantic Segmentation Networkscited by 18
  5. 2017Multi-Scale Dense Networks for Resource Efficient Image Classificationcited by 15
  6. 2019Deep Neural Network Approximation for Custom Hardware: Where We've Been, Where We're Goingcited by 13
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  8. 2019A Novel Design of Adaptive and Hierarchical Convolutional Neural Networks using Partial Reconfiguration on FPGAcited by 6
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Cited by year

Citing papers per year: 2025: 3.

3 papers.

  1. 2025A Survey on Dynamic Neural Networks: from Computer Vision to Multi-modal Sensor Fusioncited by 5
  2. 2025FPGA-based Acceleration for Convolutional Neural Networks: A Comprehensive Reviewcited by 1
  3. 2025Hardware-Algorithm Co-Optimization of Early-Exit Neural Networks for Multi-Core Edge Acceleratorscited by 0

Similar, not cited

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  1. 2025AEBNAS: Strengthening Exit Branches in Early-Exit Networks through Hardware-Aware Neural Architecture Search
  2. 2021A Competitive Edge: Can FPGAs Beat GPUs at DCNN Inference Acceleration in Resource-Limited Edge Computing Applications?
  3. 2022Fluid Batching: Exit-Aware Preemptive Serving of Early-Exit Neural Networks on Edge NPUs
  4. 2022Resource-Constrained Edge AI with Early Exit Prediction
  5. 2025A Scalable FPGA Architecture With Adaptive Memory Utilization for GEMM-Based Operations
  6. 2026SNAC-Pack 2.0: Scaled-Out Surrogate Neural Architecture Codesign
  7. 2022Pruning Early Exit Networks
  8. 2026A Comparative Study of CNN Optimization Methods for Edge AI: Exploring the Role of Early Exits