mlsanityData to 14 Oct 2026

MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning

arXiv 2407.18110 ↗First posted 25 Jul 2024cs.AR cs.AIcited by 4

On the map: Deep reinforcement learning methods → RL for energy, networks and operations

Abstract (arXiv)

Technology mapping involves mapping logical circuits to a library of cells. Traditionally, the full technology library is used, leading to a large search space and potential overhead. Motivated by randomly sampled technology mapping case studies, we propose MapTune framework that addresses this challenge by utilizing reinforcement learning to make design-specific choices during cell selection. By learning from the environment, MapTune refines the cell selection process, resulting in a reduced search space and potentially improved mapping quality. The effectiveness of MapTune is evaluated on a wide range of benchmarks, different technology libraries and technology mappers. The experimental results demonstrate that MapTune achieves higher mapping accuracy and reducing delay/area across diverse circuit designs, technology libraries and mappers. The paper also discusses the Pareto-Optimal exploration and confirms the perpetual delay-area trade-off. Conducted on benchmark suites ISCAS 85/89, ITC/ISCAS 99, VTR8.0 and EPFL benchmarks, the post-technology mapping and post-sizing quality-of-results (QoR) have been significantly improved, with average Area-Delay Product (ADP) improvement of 22.54% among all different exploration settings in MapTune. The improvements are consistently remained for four different technologies (7nm, 45nm, 130nm, and 180 nm) and two different mappers.

Key facts. Cited by 4 papers in the map (data through 14 Oct 2026). Placed in RL for energy, networks and operations, one of 15 directions in Deep reinforcement learning methods. Builds on 9 of its 53 references that are in the map. First posted on arXiv 25 Jul 2024.

Builds on

9 of 53 references.

References · 9

  1. 2015Deep Reinforcement Learning with Double Q-learningcited by 1,745
  2. 2020Chip Placement with Deep Reinforcement Learningcited by 83
  3. 2014Algorithms for multi-armed bandit problemscited by 64
  4. 2019DRiLLS: Deep Reinforcement Learning for Logic Synthesiscited by 47
  5. 2018Developing Synthesis Flows Without Human Knowledgecited by 29
  6. 2019Painting on Placement: Forecasting Routing Congestion using Conditional Generative Adversarial Netscited by 8
  7. 2021NVCell: Standard Cell Layout in Advanced Technology Nodes with Reinforcement Learningcited by 7
  8. 2019Approximate Logic Synthesis: A Reinforcement Learning-Based Technology Mapping Approachcited by 6
  9. 2024BoolGebra: Attributed Graph-learning for Boolean Algebraic Manipulationcited by 2

Built on by

Cited by year (2026 to 14 Oct)

Citing papers per year: 2025: 3; 2026: 1.

4 papers.

  1. 2025DeepCell: Self-Supervised Multiview Fusion for Circuit Representation Learningcited by 3
  2. 2025e-boost: Boosted E-Graph Extraction with Adaptive Heuristics and Exact Solvingcited by 2
  3. 2025Revisit Choice Network for Synthesis and Technology Mappingcited by 0
  4. 2026TOPCELL: Topology Optimization of Standard Cell via LLMscited by 0

Similar, not cited

Close in wording, no citation either way

  1. 2024Retrieval-Guided Reinforcement Learning for Boolean Circuit Minimization
  2. 2026AstRL: Analog and Mixed-Signal Circuit Synthesis with Deep Reinforcement Learning
  3. 2024GraCo -- A Graph Composer for Integrated Circuits
  4. 2026CLDRoute: Conditional Latent Diffusion for Routability Map Generation in Physical Design
  5. 2023INVICTUS: Optimizing Boolean Logic Circuit Synthesis via Synergistic Learning and Search
  6. 2024CircuitVAE: Efficient and Scalable Latent Circuit Optimization
  7. 2026Simulation-Aware In-Context Policy Improvement for LLM-Aided Analog Layout Refinement
  8. 2024Improving Parallel Program Performance with LLM Optimizers via Agent-System Interfaces