Efficient Stimuli Generation using Reinforcement Learning in Design Verification
On the map: Deep reinforcement learning methods → RL training of language and agent models
Abstract (arXiv)
The increasing design complexity of System-on-Chips (SoCs) has led to significant verification challenges, particularly in meeting coverage targets within a timely manner. At present, coverage closure is heavily dependent on constrained random and coverage driven verification methodologies where the randomized stimuli are bounded to verify certain scenarios and to reach coverage goals. This process is said to be exhaustive and to consume a lot of project time. In this paper, a novel methodology is proposed to generate efficient stimuli with the help of Reinforcement Learning (RL) to reach the maximum code coverage of the Design Under Verification (DUV). Additionally, an automated framework is created using metamodeling to generate a SystemVerilog testbench and an RL environment for any given design. The proposed approach is applied to various designs and the produced results proves that the RL agent provides effective stimuli to achieve code coverage faster in comparison with baseline random simulations. Furthermore, various RL agents and reward schemes are analyzed in our work.
Key facts. Cited by 5 papers in the map (data through 14 Oct 2026). Placed in RL training of language and agent models, one of 15 directions in Deep reinforcement learning methods. Builds on 4 of its 22 references that are in the map. First posted on arXiv 30 May 2024.
Builds on
4 of 22 references.
References · 4
- 2019Optimizing Design Verification using Machine Learning: Doing better than Randomcited by 8
- 2022Using Neural Networks for Novelty-based Test Selection to Accelerate Functional Coverage Closurecited by 5
- 2020Optimising Design Verification Using Machine Learning: An Open Source Solutioncited by 4
- 2021VeRLPy: Python Library for Verification of Digital Designs with Reinforcement Learningcited by 3
Built on by
Citing papers per year: 2025: 3; 2026: 2.
5 papers.
- 2026HAVEN: Hybrid Automated Verification ENgine for UVM Testbench Synthesis with LLMscited by 2
- 2025Review of Machine Learning for Micro-Electronic Design Verificationcited by 1
- 2025Optimizing Coverage-Driven Verification Using Machine Learning and PyUVM: A Novel Approachcited by 0
- 2025RIFT: A Scalable Methodology for LLM Accelerator Fault Assessment using Reinforcement Learningcited by 0
- 2026Formal-Verification-Guided Bayesian Optimization for Non-Intrusive Last-Mile Coverage Closurecited by 0
- 2026Formal-Verification-Guided Bayesian Optimization for Non-Intrusive Last-Mile Coverage Closure12 Oct 2026
- 2026HAVEN: Hybrid Automated Verification ENgine for UVM Testbench Synthesis with LLMs30 Apr 2026
- 2025RIFT: A Scalable Methodology for LLM Accelerator Fault Assessment using Reinforcement Learning10 Dec 2025
- 2025Review of Machine Learning for Micro-Electronic Design Verification5 Mar 2025
- 2025Optimizing Coverage-Driven Verification Using Machine Learning and PyUVM: A Novel Approach23 Feb 2025
Similar, not cited
Close in wording, no citation either way
- 2026CovR: Coverage-Aware Hardware Verification via Reasoning-Guided Reinforcement Learning
- 2026EvolveGen: Algorithmic Level Hardware Model Checking Benchmark Generation through Reinforcement Learning
- 2026BEHAVE: Functional Behavior Modeling Enables Self-Improving Agents for Hardware Design and Verification
- 2026GRPO with State Mutations: Improving LLM-Based Hardware Test Plan Generation
- 2025TB or Not TB: Coverage-Driven Direct Preference Optimization for Verilog Stimulus Generation
- 2026AgentDV: Closed-Loop Agentic AI for Hardware Design Verification
- 2025AUTOCIRCUIT-RL: Reinforcement Learning-Driven LLM for Automated Circuit Topology Generation
- 2023INVICTUS: Optimizing Boolean Logic Circuit Synthesis via Synergistic Learning and Search