GoGoTB: Agentic RTL Verification with Specification-Grounded Coverage Closure
On the map: LLM agents and tool use → Software engineering coding agents
Abstract (arXiv)
Functional verification dominates integrated circuit (IC) front-end engineering effort, and a single missed bug that escapes to silicon can trigger a costly respin. Recent large language models (LLMs) offer new opportunities to automate this process, yet existing LLM-based approaches generate each component through independent single-turn calls with no shared context, leaving interface mismatches undetected and reported coverage disconnected from specification requirements. To address these challenges, we present GoGoTB, an agentic framework that achieves end-to-end verification closure through three subsystems: an agentic execution control layer, an evolvable knowledge system, and specification-grounded coverage closure. The execution control layer separates deterministic enforcement from LLM reasoning at every tool and stage boundary. The knowledge system dispatches methodology and design-specific expertise on demand. The coverage framework anchors every bin to a named specification behavior so that each residual gap has a diagnosable root cause and a targeted remedy. Tested on 8 register transfer level (RTL) designs without any human intervention, GoGoTB achieves 100% environment generation success and averages 98.4% line, 97.2% branch, 97.0% toggle, and 83.2% functional coverage. No prior work successfully generates a complete verification environment or achieves meaningful coverage on the same benchmarks.
Key facts. Cited by 1 paper in the map (data through 14 Oct 2026). Placed in Software engineering coding agents, one of 16 directions in LLM agents and tool use. Builds on 9 of its 24 references that are in the map. First posted on arXiv 28 Jul 2026.
Builds on
9 of 24 references.
References · 9
- 2023Reflexion: Language Agents with Verbal Reinforcement Learningcited by 4,276
- 2023A Survey on Large Language Model based Autonomous Agentscited by 2,242
- 2024AutoBench: Automatic Testbench Generation and Evaluation Using LLMs for HDL Designcited by 41
- 2024AssertLLM: Generating Hardware Verification Assertions from Design Specifications via Multi-LLMscited by 31
- 2024CorrectBench: Automatic Testbench Generation with Functional Self-Correction using LLMs for HDL Designcited by 24
- 2023Using LLMs to Facilitate Formal Verification of RTLcited by 18
- 2024UVLLM: An Automated Universal RTL Verification Framework using LLMscited by 17
- 2025From Concept to Practice: an Automated LLM-aided UVM Machine for RTL Verificationcited by 9
- 2025Spec2Assertion: Automatic Pre-RTL Assertion Generation using Large Language Models with Progressive Regularizationcited by 8
Built on by
Citing papers per year: 2026: 1.
1 paper.
Similar, not cited
Close in wording, no citation either way
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- 2026Open-Source LLM-Driven Formal Verification: A Multi-Agent Pipeline for RTL Repair
- 2026Veri-Sure: A Contract-Aware Multi-Agent Framework with Temporal Tracing and Formal Verification for Correct RTL Code Generation
- 2026Agentic AI-based Coverage Closure for Formal Verification
- 2026ACE-RTL: When Agentic Context Evolution Meets RTL-Specialized LLMs
- 2026A Survey on LLM-Integrated Hardware Design Verification
- 2026Shift-Left High-Level Synthesis Verification via Knowledge-Augmented LLM Agent ↗
- 2025ASIC-Agent: An Autonomous Multi-Agent System for ASIC Design with Benchmark Evaluation