SpecAlign: A Semantic Alignment Framework for SystemVerilog Assertion Generation
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Abstract (arXiv)
Existing Large Language Model (LLM) approaches to SystemVerilog Assertion (SVA) generation primarily focus on syntactic validity and formal verification outcomes, while semantic alignment between generated assertions and natural language specifications remains difficult to quantify. As a result, hallucinated or misaligned SVAs can reduce confidence and increase debugging efforts in the absence of golden RTL. This paper presents SpecAlign, a framework for semantic evaluation and refinement of LLM-generated SVAs. SpecAlign introduces two iterative alignment loops that assess both natural language properties and SVAs against the design specification using entailment-based classification. We improve alignment decisions by generating multiple reasoning paths using chain-of-thought prompting and aggregating them via a self-consistency voting mechanism. Misaligned assertions are analyzed to generate actionable feedback for refinement. We further define a quantitative alignment score to measure semantic consistency across iterations. Experimental results demonstrate that SpecAlign effectively detects semantic inconsistencies and improves assertion alignment without relying on golden RTL, providing a scalable complement to traditional formal verification evaluation metrics.
Key facts. Cited by 1 paper in the map (data through 14 Oct 2026). Builds on 11 of its 16 references that are in the map. First posted on arXiv 24 May 2026.
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11 of 16 references.
References · 11
- 2022Self-Consistency Improves Chain of Thought Reasoning in Language Modelscited by 5,708
- 2023Self-Refine: Iterative Refinement with Self-Feedbackcited by 3,442
- 2022Survey of Hallucination in Natural Language Generationcited by 2,075
- 2024AssertLLM: Generating Hardware Verification Assertions from Design Specifications via Multi-LLMscited by 31
- 2024ChIRAAG: ChatGPT Informed Rapid and Automated Assertion Generationcited by 16
- 2025AssertionForge: Enhancing Formal Verification Assertion Generation with Structured Representation of Specifications and RTLcited by 13
- 2024All Artificial, Less Intelligence: GenAI through the Lens of Formal Verificationcited by 11
- 2025Spec2Assertion: Automatic Pre-RTL Assertion Generation using Large Language Models with Progressive Regularizationcited by 8
- 2025AssertGen: Enhancement of LLM-aided Assertion Generation through Cross-Layer Signal Bridgingcited by 5
- 2025AssertCoder: LLM-Based Assertion Generation via Multimodal Specification Extractioncited by 4
- 2025SANGAM: SystemVerilog Assertion Generation via Monte Carlo Tree Self-Refinecited by 2
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Citing papers per year: 2026: 1.
1 paper.
- 2026A Survey on LLM-Integrated Hardware Design Verificationcited by 0
- 2026A Survey on LLM-Integrated Hardware Design Verification6 Oct 2026
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- 2025VeriEquivBench: An Equivalence Score for Ground-Truth-Free Evaluation of Formally Verifiable Code
- 2026SpecAlign: Efficient Specification-Grounded Alignment of Large Language Models via Synthetic Data
- 2026From Language to Logic: Bridging LLMs & Formal Representations for RTL Assertion Generation
- 2026QiMeng-CodeV-SVA: Training Specialized LLMs for Hardware Assertion Generation via RTL-Grounded Bidirectional Data Synthesis
- 2025Reasoning over Boundaries: Enhancing Specification Alignment via Test-time Deliberation
- 2025Hybrid-NL2SVA: Integrating RAG and Finetuning for LLM-based NL2SVA
- 2026Detecting Inconsistencies in Model Specifications with LLM-as-Verifier Reasoning
- 2026SHADOWBENCH: Toward Reliable Automatic Evaluation of Semantic Alignment in Autoformalization