mlsanityData to 7 Oct 2026

SWIM: Selective Write-Verify for Computing-in-Memory Neural Accelerators

arXiv 2202.08395 ↗First posted 17 Feb 2022cs.LGcited by 16

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Abstract (arXiv)

Computing-in-Memory architectures based on non-volatile emerging memories have demonstrated great potential for deep neural network (DNN) acceleration thanks to their high energy efficiency. However, these emerging devices can suffer from significant variations during the mapping process i.e., programming weights to the devices), and if left undealt with, can cause significant accuracy degradation. The non-ideality of weight mapping can be compensated by iterative programming with a write-verify scheme, i.e., reading the conductance and rewriting if necessary. In all existing works, such a practice is applied to every single weight of a DNN as it is being mapped, which requires extensive programming time. In this work, we show that it is only necessary to select a small portion of the weights for write-verify to maintain the DNN accuracy, thus achieving significant speedup. We further introduce a second derivative based technique SWIM, which only requires a single pass of forward and backpropagation, to efficiently select the weights that need write-verify. Experimental results on various DNN architectures for different datasets show that SWIM can achieve up to 10x programming speedup compared with conventional full-blown write-verify while attaining a comparable accuracy.

Key facts. Cited by 16 papers in the map (data through 7 Oct 2026). Builds on 6 of its 13 references that are in the map. First posted on arXiv 17 Feb 2022.

Builds on

6 of 13 references.

References · 6

  1. 2015Deep Residual Learning for Image Recognitioncited by 51,809
  2. 2017Efficient Processing of Deep Neural Networks: A Tutorial and Surveycited by 427
  3. 2019Device-Circuit-Architecture Co-Exploration for Computing-in-Memory Neural Acceleratorscited by 32
  4. 2021Uncertainty Modeling of Emerging Device-based Computing-in-Memory Neural Accelerators with Application to Neural Architecture Searchcited by 17
  5. 2019When Single Event Upset Meets Deep Neural Networks: Observations, Explorations, and Remediescited by 14
  6. 2021RADARS: Memory Efficient Reinforcement Learning Aided Differentiable Neural Architecture Searchcited by 8

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Cited by year (2026 to 7 Oct)

Citing papers per year: 2022: 1; 2023: 6; 2024: 4; 2025: 2; 2026: 3.

16 papers.

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  1. 2022Computing-In-Memory Neural Network Accelerators for Safety-Critical Systems: Can Small Device Variations Be Disastrous?cited by 12
  2. 2024Robust Implementation of Retrieval-Augmented Generation on Edge-based Computing-in-Memory Architecturescited by 12
  3. 2023On the Viability of using LLMs for SW/HW Co-Design: An Example in Designing CiM DNN Acceleratorscited by 11
  4. 2024FL-NAS: Towards Fairness of NAS for Resource Constrained Devices via Large Language Modelscited by 9
  5. 2023Improving Realistic Worst-Case Performance of NVCiM DNN Accelerators through Training with Right-Censored Gaussian Noisecited by 8
  6. 2024TSB: Tiny Shared Block for Efficient DNN Deployment on NVCIM Acceleratorscited by 3
  7. 2023NeFT: Negative Feedback Training to Improve Robustness of Compute-In-Memory DNN Acceleratorscited by 2
  8. 2023Compute-in-Memory based Neural Network Accelerators for Safety-Critical Systems: Worst-Case Scenarios and Protectionscited by 2
  9. 2024Zero-Space Cost Fault Tolerance for Transformer-based Language Models on ReRAMcited by 2
  10. 2025HaLoRA: Hardware-aware Low-Rank Adaptation for Large Language Models Based on Hybrid Compute-in-Memory Architecturecited by 2
  11. 2023TinyML Design Contest for Life-Threatening Ventricular Arrhythmia Detectioncited by 1
  12. 2026When Small Variations Become Big Failures: Reliability Challenges in Compute-in-Memory Neural Acceleratorscited by 1
4 more
  1. 2023U-SWIM: Universal Selective Write-Verify for Computing-in-Memory Neural Acceleratorscited by 0
  2. 2025FedLAM: Low-latency Wireless Federated Learning via Layer-wise Adaptive Modulationcited by 0
  3. 2026CiMRAG: CiM-Aware Domain-Adaptive and Noise-Resilient Retrieval-Augmented Generation for Edge-Based LLMscited by 0
  4. 2026Interface-Aware KV Cache Quantization for Dense On-Chip NVM in Long-Context LLM Decodingcited by 0