mlsanityData to 14 Oct 2026

Computing-In-Memory Neural Network Accelerators for Safety-Critical Systems: Can Small Device Variations Be Disastrous?

arXiv 2207.07626 ↗First posted 15 Jul 2022cs.AR cs.LGcited by 12

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Abstract (arXiv)

Computing-in-Memory (CiM) architectures based on emerging non-volatile memory (NVM) devices have demonstrated great potential for deep neural network (DNN) acceleration thanks to their high energy efficiency. However, NVM devices suffer from various non-idealities, especially device-to-device variations due to fabrication defects and cycle-to-cycle variations due to the stochastic behavior of devices. As such, the DNN weights actually mapped to NVM devices could deviate significantly from the expected values, leading to large performance degradation. To address this issue, most existing works focus on maximizing average performance under device variations. This objective would work well for general-purpose scenarios. But for safety-critical applications, the worst-case performance must also be considered. Unfortunately, this has been rarely explored in the literature. In this work, we formulate the problem of determining the worst-case performance of CiM DNN accelerators under the impact of device variations. We further propose a method to effectively find the specific combination of device variation in the high-dimensional space that leads to the worst-case performance. We find that even with very small device variations, the accuracy of a DNN can drop drastically, causing concerns when deploying CiM accelerators in safety-critical applications. Finally, we show that surprisingly none of the existing methods used to enhance average DNN performance in CiM accelerators are very effective when extended to enhance the worst-case performance, and further research down the road is needed to address this problem.

Key facts. Cited by 12 papers in the map (data through 14 Oct 2026). Builds on 16 of its 42 references that are in the map. First posted on arXiv 15 Jul 2022.

Builds on

16 of 42 references.

References · 16

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  5. 2020Co-Exploration of Neural Architectures and Heterogeneous ASIC Accelerator Designs Targeting Multiple Taskscited by 43
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  7. 2021Formalizing Generalization and Robustness of Neural Networks to Weight Perturbationscited by 22
  8. 2022The Larger The Fairer? Small Neural Networks Can Achieve Fairness for Edge Devicescited by 21
  9. 2021Uncertainty Modeling of Emerging Device-based Computing-in-Memory Neural Accelerators with Application to Neural Architecture Searchcited by 17
  10. 2022SWIM: Selective Write-Verify for Computing-in-Memory Neural Acceleratorscited by 16
  11. 2019When Single Event Upset Meets Deep Neural Networks: Observations, Explorations, and Remediescited by 15
  12. 2022Efficient Global Robustness Certification of Neural Networks via Interleaving Twin-Network Encodingcited by 15
4 more
  1. 2021Can Noise on Qubits Be Learned in Quantum Neural Network? A Case Study on QuantumFlowcited by 13
  2. 2021Exploration of Quantum Neural Architecture by Mixing Quantum Neuron Designscited by 11
  3. 2021RADARS: Memory Efficient Reinforcement Learning Aided Differentiable Neural Architecture Searchcited by 8
  4. 2022A Semi-Decoupled Approach to Fast and Optimal Hardware-Software Co-Design of Neural Acceleratorscited by 1

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Cited by year (2026 to 14 Oct)

Citing papers per year: 2023: 5; 2024: 1; 2025: 0; 2026: 6.

12 papers.

  1. 2023On the Viability of using LLMs for SW/HW Co-Design: An Example in Designing CiM DNN Acceleratorscited by 11
  2. 2023Improving Realistic Worst-Case Performance of NVCiM DNN Accelerators through Training with Right-Censored Gaussian Noisecited by 8
  3. 2023Compute-in-Memory based Neural Network Accelerators for Safety-Critical Systems: Worst-Case Scenarios and Protectionscited by 3
  4. 2023NeFT: Negative Feedback Training to Improve Robustness of Compute-In-Memory DNN Acceleratorscited by 2
  5. 2024Zero-Space Cost Fault Tolerance for Transformer-based Language Models on ReRAMcited by 2
  6. 2026When Small Variations Become Big Failures: Reliability Challenges in Compute-in-Memory Neural Acceleratorscited by 1
  7. 2023U-SWIM: Universal Selective Write-Verify for Computing-in-Memory Neural Acceleratorscited by 0
  8. 2026Formally Verifying Analog Neural Networks Under Process Variations Using Polynomial Zonotopescited by 0
  9. 2026Selective KV Cache Protection for Noise-Resilient LLM Inference on Analog Compute-In-Memory Systemscited by 0
  10. 2026ASSERT: Adaptive Stochastic Sampling for Robust Diffusion Models on Analog Compute-in-Memory Hardwarecited by 0
  11. 2026Interface-Aware KV Cache Quantization for Dense On-Chip NVM in Long-Context LLM Decodingcited by 0
  12. 2026NNV3: Expanding Neural Network Verification to New Architectures and Domainscited by 0