When Single Event Upset Meets Deep Neural Networks: Observations, Explorations, and Remedies
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Abstract (arXiv)
Deep Neural Network has proved its potential in various perception tasks and hence become an appealing option for interpretation and data processing in security sensitive systems. However, security-sensitive systems demand not only high perception performance, but also design robustness under various circumstances. Unlike prior works that study network robustness from software level, we investigate from hardware perspective about the impact of Single Event Upset (SEU) induced parameter perturbation (SIPP) on neural networks. We systematically define the fault models of SEU and then provide the definition of sensitivity to SIPP as the robustness measure for the network. We are then able to analytically explore the weakness of a network and summarize the key findings for the impact of SIPP on different types of bits in a floating point parameter, layer-wise robustness within the same network and impact of network depth. Based on those findings, we propose two remedy solutions to protect DNNs from SIPPs, which can mitigate accuracy degradation from 28% to 0.27% for ResNet with merely 0.24-bit SRAM area overhead per parameter.
Key facts. Cited by 14 papers in the map (data through 7 Oct 2026). First posted on arXiv 10 Sep 2019.
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Citing papers per year: 2021: 1; 2022: 2; 2023: 6; 2024: 3; 2025: 1; 2026: 1.
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- 2023A Systematic Literature Review on Hardware Reliability Assessment Methods for Deep Neural Networkscited by 23
- 2021Uncertainty Modeling of Emerging Device-based Computing-in-Memory Neural Accelerators with Application to Neural Architecture Searchcited by 17
- 2022SWIM: Selective Write-Verify for Computing-in-Memory Neural Acceleratorscited by 16
- 2022Computing-In-Memory Neural Network Accelerators for Safety-Critical Systems: Can Small Device Variations Be Disastrous?cited by 12
- 2023On the Viability of using LLMs for SW/HW Co-Design: An Example in Designing CiM DNN Acceleratorscited by 11
- 2023Improving Realistic Worst-Case Performance of NVCiM DNN Accelerators through Training with Right-Censored Gaussian Noisecited by 8
- 2024Evaluating Single Event Upsets in Deep Neural Networks for Semantic Segmentation: an embedded system perspectivecited by 8
- 2023Resilience of Deep Learning applications: a systematic literature review of analysis and hardening techniquescited by 4
- 2024LLMSat: A Large Language Model-Based Goal-Oriented Agent for Autonomous Space Explorationcited by 3
- 2023Compute-in-Memory based Neural Network Accelerators for Safety-Critical Systems: Worst-Case Scenarios and Protectionscited by 2
- 2024DeepVigor+: Scalable and Accurate Semi-Analytical Fault Resilience Analysis for Deep Neural Networkcited by 1
- 2026PhD Thesis Summary: Methods for Reliability Assessment and Enhancement of Deep Neural Network Hardware Acceleratorscited by 1
- 2026PhD Thesis Summary: Methods for Reliability Assessment and Enhancement of Deep Neural Network Hardware Accelerators17 Feb 2026
- 2025Efficient Triple Modular Redundancy for Reliability Enhancement of DNNs Using Explainable AI4 Jul 2025
- 2024Evaluating Single Event Upsets in Deep Neural Networks for Semantic Segmentation: an embedded system perspective4 Dec 2024
- 2024DeepVigor+: Scalable and Accurate Semi-Analytical Fault Resilience Analysis for Deep Neural Network21 Oct 2024
- 2024LLMSat: A Large Language Model-Based Goal-Oriented Agent for Autonomous Space Exploration13 Apr 2024
- 2023U-SWIM: Universal Selective Write-Verify for Computing-in-Memory Neural Accelerators11 Dec 2023
- 2023Compute-in-Memory based Neural Network Accelerators for Safety-Critical Systems: Worst-Case Scenarios and Protections11 Dec 2023
- 2023Resilience of Deep Learning applications: a systematic literature review of analysis and hardening techniques27 Sep 2023
- 2023Improving Realistic Worst-Case Performance of NVCiM DNN Accelerators through Training with Right-Censored Gaussian Noise29 Jul 2023
- 2023On the Viability of using LLMs for SW/HW Co-Design: An Example in Designing CiM DNN Accelerators12 Jun 2023
- 2023A Systematic Literature Review on Hardware Reliability Assessment Methods for Deep Neural Networks9 May 2023
- 2022Computing-In-Memory Neural Network Accelerators for Safety-Critical Systems: Can Small Device Variations Be Disastrous?15 Jul 2022
- 2023A Systematic Literature Review on Hardware Reliability Assessment Methods for Deep Neural Networkscited by 23
- 2021Uncertainty Modeling of Emerging Device-based Computing-in-Memory Neural Accelerators with Application to Neural Architecture Searchcited by 17
- 2022SWIM: Selective Write-Verify for Computing-in-Memory Neural Acceleratorscited by 16
- 2022Computing-In-Memory Neural Network Accelerators for Safety-Critical Systems: Can Small Device Variations Be Disastrous?cited by 12
- 2023On the Viability of using LLMs for SW/HW Co-Design: An Example in Designing CiM DNN Acceleratorscited by 11
- 2023Improving Realistic Worst-Case Performance of NVCiM DNN Accelerators through Training with Right-Censored Gaussian Noisecited by 8
- 2024Evaluating Single Event Upsets in Deep Neural Networks for Semantic Segmentation: an embedded system perspectivecited by 8
- 2023Resilience of Deep Learning applications: a systematic literature review of analysis and hardening techniquescited by 4
- 2023Compute-in-Memory based Neural Network Accelerators for Safety-Critical Systems: Worst-Case Scenarios and Protectionscited by 2
- 2024DeepVigor+: Scalable and Accurate Semi-Analytical Fault Resilience Analysis for Deep Neural Networkcited by 1
- 2026PhD Thesis Summary: Methods for Reliability Assessment and Enhancement of Deep Neural Network Hardware Acceleratorscited by 1
- 2023U-SWIM: Universal Selective Write-Verify for Computing-in-Memory Neural Acceleratorscited by 0
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- 2026PhD Thesis Summary: Methods for Reliability Assessment and Enhancement of Deep Neural Network Hardware Accelerators17 Feb 2026
- 2025Efficient Triple Modular Redundancy for Reliability Enhancement of DNNs Using Explainable AI4 Jul 2025
- 2024Evaluating Single Event Upsets in Deep Neural Networks for Semantic Segmentation: an embedded system perspective4 Dec 2024
- 2024DeepVigor+: Scalable and Accurate Semi-Analytical Fault Resilience Analysis for Deep Neural Network21 Oct 2024
- 2023U-SWIM: Universal Selective Write-Verify for Computing-in-Memory Neural Accelerators11 Dec 2023
- 2023Compute-in-Memory based Neural Network Accelerators for Safety-Critical Systems: Worst-Case Scenarios and Protections11 Dec 2023
- 2023Resilience of Deep Learning applications: a systematic literature review of analysis and hardening techniques27 Sep 2023
- 2023Improving Realistic Worst-Case Performance of NVCiM DNN Accelerators through Training with Right-Censored Gaussian Noise29 Jul 2023
- 2023On the Viability of using LLMs for SW/HW Co-Design: An Example in Designing CiM DNN Accelerators12 Jun 2023
- 2023A Systematic Literature Review on Hardware Reliability Assessment Methods for Deep Neural Networks9 May 2023
- 2022Computing-In-Memory Neural Network Accelerators for Safety-Critical Systems: Can Small Device Variations Be Disastrous?15 Jul 2022
- 2022SWIM: Selective Write-Verify for Computing-in-Memory Neural Accelerators17 Feb 2022
12 newest of 13 All 13 (JSON)