MATCHA: Efficient Deployment of Deep Neural Networks on Multi-Accelerator Heterogeneous Edge SoCs
Not on the map. Why?
Abstract (arXiv)
Deploying DNNs on System-on-Chips (SoC) with multiple heterogeneous acceleration engines is challenging, and the majority of deployment frameworks cannot fully exploit heterogeneity. We present MATCHA, a unified DNN deployment framework that generates highly concurrent schedules for parallel, heterogeneous accelerators and uses constraint programming to optimize L3/L2 memory allocation and scheduling. Using pattern matching, tiling, and mapping across individual HW units enables parallel execution and high accelerator utilization. On the MLPerf Tiny benchmark, using a SoC with two heterogeneous accelerators, MATCHA improves accelerator utilization and reduces inference latency by up to 35% with respect to the the state-of-the-art MATCH compiler.
Key facts. No citing papers in the map yet (data through 7 Oct 2026). Builds on 16 of its 33 references that are in the map. First posted on arXiv 10 Apr 2026.
Builds on
16 of 33 references.
References · 16
- 2017Attention Is All You Needcited by 59,932
- 2015Deep Residual Learning for Image Recognitioncited by 51,809
- 2016Aggregated Residual Transformations for Deep Neural Networkscited by 2,540
- 2018Demystifying Parallel and Distributed Deep Learning: An In-Depth Concurrency Analysiscited by 154
- 2021MLPerf Tiny Benchmarkcited by 118
- 2019Gemmini: Enabling Systematic Deep-Learning Architecture Evaluation via Full-Stack Integrationcited by 59
- 2018Interstellar: Using Halide's Scheduling Language to Analyze DNN Acceleratorscited by 33
- 2021Bolt: Bridging the Gap between Auto-tuners and Hardware-native Performancecited by 18
- 2024Flex-PE: Flexible and SIMD Multi-Precision Processing Element for AI Workloadscited by 15
- 2024Deeploy: Enabling Energy-Efficient Deployment of Small Language Models On Heterogeneous Microcontrollerscited by 11
- 2023Map-and-Conquer: Energy-Efficient Mapping of Dynamic Neural Nets onto Heterogeneous MPSoCscited by 9
- 2023Cheshire: A Lightweight, Linux-Capable RISC-V Host Platform for Domain-Specific Accelerator Plug-Incited by 7
4 more
- 2024MATCH: Model-Aware TVM-based Compilation for Heterogeneous Edge Devicescited by 5
- 2023Spatz: Clustering Compact RISC-V-Based Vector Units to Maximize Computing Efficiencycited by 3
- 2024HTVM: Efficient Neural Network Deployment On Heterogeneous TinyML Platformscited by 3
- 2023Hybrid Modular Redundancy: Exploring Modular Redundancy Approaches in RISC-V Multi-Core Computing Clusters for Reliable Processing in Spacecited by 1
Built on by
Not cited yet.