mlsanityData to 7 Oct 2026

NVR: Vector Runahead on NPUs for Sparse Memory Access

arXiv 2502.13873 ↗First posted 19 Feb 2025cs.AR cs.AIcited by 0

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Abstract (arXiv)

Deep Neural Networks are increasingly leveraging sparsity to reduce the scaling up of model parameter size. However, reducing wall-clock time through sparsity and pruning remains challenging due to irregular memory access patterns, leading to frequent cache misses. In this paper, we present NPU Vector Runahead (NVR), a prefetching mechanism tailored for NPUs to address cache miss problems in sparse DNN workloads. Rather than optimising memory patterns with high overhead and poor portability, NVR adapts runahead execution to the unique architecture of NPUs. NVR provides a general micro-architectural solution for sparse DNN workloads without requiring compiler or algorithmic support, operating as a decoupled, speculative, lightweight hardware sub-thread alongside the NPU, with minimal hardware overhead (under 5%). NVR achieves an average 90% reduction in cache misses compared to SOTA prefetching in general-purpose processors, delivering 4x average speedup on sparse workloads versus NPUs without prefetching. Moreover, we investigate the advantages of incorporating a small cache (16KB) into the NPU combined with NVR. Our evaluation shows that expanding this modest cache delivers 5x higher performance benefits than increasing the L2 cache size by the same amount.

Key facts. No citing papers in the map yet (data through 7 Oct 2026). Builds on 17 of its 43 references that are in the map. First posted on arXiv 19 Feb 2025.

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17 of 43 references.

References · 17

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  12. 2024Post-Training Sparse Attention with Double Sparsitycited by 45
5 more
  1. 2018Balanced Sparsity for Efficient DNN Inference on GPUcited by 27
  2. 2021PointAcc: Efficient Point Cloud Acceleratorcited by 23
  3. 2019SMASH: Co-designing Software Compression and Hardware-Accelerated Indexing for Efficient Sparse Matrix Operationscited by 7
  4. 2019Integrating NVIDIA Deep Learning Accelerator (NVDLA) with RISC-V SoC on FireSimcited by 4
  5. 2024Multimodal joint prediction of traffic spatial-temporal data with graph sparse attention mechanism and bidirectional temporal convolutional networkcited by 2

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