mlsanityData to 7 Oct 2026

A High-Level Compiler Integration Approach for Deep Learning Accelerators Supporting Abstraction and Optimization

arXiv 2507.04828 ↗First posted 7 Jul 2025cs.LGcited by 0

Not on the map. Why?

Abstract (arXiv)

The growing adoption of domain-specific architectures in edge computing platforms for deep learning has highlighted the efficiency of hardware accelerators. However, integrating custom accelerators into modern machine learning (ML) compilers remains a complex challenge due to the need for significant modifications in compilation layers and specialized scheduling techniques. Existing frameworks offer partial solutions and require users to navigate intricate compiler internals. In this paper, we introduce a TVM-based compilation integration approach that targets GEMM-based deep learning accelerators. Our approach abstracts the complexities of compiler integration, enabling seamless integration of accelerators without requiring in-depth knowledge of the underlying compiler. Furthermore, we extend and incorporate design space exploration tools, specifically CoSA, to automate efficient tensor scheduling, accounting for factors such as uneven mapping and double buffering. Our framework is benchmarked on the Gemmini accelerator, demonstrating performance comparable to its specialized manually implemented toolchain.

Key facts. No citing papers in the map yet (data through 7 Oct 2026). Builds on 7 of its 10 references that are in the map. First posted on arXiv 7 Jul 2025.

Builds on

7 of 10 references.

References · 7

  1. 2020Ansor: Generating High-Performance Tensor Programs for Deep Learningcited by 199
  2. 2019Gemmini: Enabling Systematic Deep-Learning Architecture Evaluation via Full-Stack Integrationcited by 59
  3. 2021CoSA: Scheduling by Constrained Optimization for Spatial Acceleratorscited by 22
  4. 2022TinyIREE: An ML Execution Environment for Embedded Systems from Compilation to Deploymentcited by 12
  5. 2021Bring Your Own Codegen to Deep Learning Compilercited by 5
  6. 2024MATCH: Model-Aware TVM-based Compilation for Heterogeneous Edge Devicescited by 5
  7. 2022Integration of a systolic array based hardware accelerator into a DNN operator auto-tuning frameworkcited by 3

Built on by

Not cited yet.