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PUMA: A Programmable Ultra-efficient Memristor-based Accelerator for Machine Learning Inference

arXiv 1901.10351 ↗First posted 29 Jan 2019cs.ET cs.ARcited by 61

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Abstract (arXiv)

Memristor crossbars are circuits capable of performing analog matrix-vector multiplications, overcoming the fundamental energy efficiency limitations of digital logic. They have been shown to be effective in special-purpose accelerators for a limited set of neural network applications. We present the Programmable Ultra-efficient Memristor-based Accelerator (PUMA) which enhances memristor crossbars with general purpose execution units to enable the acceleration of a wide variety of Machine Learning (ML) inference workloads. PUMA's microarchitecture techniques exposed through a specialized Instruction Set Architecture (ISA) retain the efficiency of in-memory computing and analog circuitry, without compromising programmability. We also present the PUMA compiler which translates high-level code to PUMA ISA. The compiler partitions the computational graph and optimizes instruction scheduling and register allocation to generate code for large and complex workloads to run on thousands of spatial cores. We have developed a detailed architecture simulator that incorporates the functionality, timing, and power models of PUMA's components to evaluate performance and energy consumption. A PUMA accelerator running at 1 GHz can reach area and power efficiency of 577~GOPS/s/mm2 and 837~GOPS/s/W, respectively. Our evaluation of diverse ML applications from image recognition, machine translation, and language modelling (5M-800M synapses) shows that PUMA achieves up to 2,446× energy and 66× latency improvement for inference compared to state-of-the-art GPUs. Compared to an application-specific memristor-based accelerator, PUMA incurs small energy overheads at similar inference latency and added programmability.

Key facts. Cited by 61 papers in the map (data through 14 Oct 2026). First posted on arXiv 29 Jan 2019.

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Citing papers per year: 2021: 10; 2022: 7; 2023: 14; 2024: 15; 2025: 10; 2026: 5.

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  1. 2023X-Former: In-Memory Acceleration of Transformerscited by 25
  2. 2023Reducing Energy Bloat in Large Model Trainingcited by 22
  3. 2024Memory Is All You Need: An Overview of Compute-in-Memory Architectures for Accelerating Large Language Model Inferencecited by 15
  4. 2021Automated Deep Learning: Neural Architecture Search Is Not the Endcited by 13
  5. 2021FORMS: Fine-grained Polarized ReRAM-based In-situ Computation for Mixed-signal DNN Acceleratorcited by 12
  6. 2023Using the IBM Analog In-Memory Hardware Acceleration Kit for Neural Network Training and Inferencecited by 11
  7. 2021GradPIM: A Practical Processing-in-DRAM Architecture for Gradient Descentcited by 10
  8. 2021On the Accuracy of Analog Neural Network Inference Acceleratorscited by 10
  9. 2022SpikeSim: An end-to-end Compute-in-Memory Hardware Evaluation Tool for Benchmarking Spiking Neural Networkscited by 9
  10. 2021AnalogNets: ML-HW Co-Design of Noise-robust TinyML Models and Always-On Analog Compute-in-Memory Acceleratorcited by 7
  11. 2022Interconnect Parasitics and Partitioning in Fully-Analog In-Memory Computing Architecturescited by 6
  12. 2021Bring Your Own Codegen to Deep Learning Compilercited by 5
38 more
  1. 2023Towards Efficient In-memory Computing Hardware for Quantized Neural Networks: State-of-the-art, Open Challenges and Perspectivescited by 5
  2. 2022MRAM-based Analog Sigmoid Function for In-memory Computingcited by 4
  3. 2023Heterogeneous Integration of In-Memory Analog Computing Architectures with Tensor Processing Unitscited by 4
  4. 2021Efficiency-driven Hardware Optimization for Adversarially Robust Neural Networkscited by 3
  5. 2021NAX: Co-Designing Neural Network and Hardware Architecture for Memristive Xbar based Computing Systemscited by 3
  6. 2024CIM-MLC: A Multi-level Compilation Stack for Computing-In-Memory Acceleratorscited by 3
  7. 2024Reducing the Barriers to Entry for Foundation Model Trainingcited by 3
  8. 2024BF-IMNA: A Bit Fluid In-Memory Neural Architecture for Neural Network Accelerationcited by 3
  9. 2022An Experimental Evaluation of Machine Learning Training on a Real Processing-in-Memory Systemcited by 2
  10. 2024HCiM: ADC-Less Hybrid Analog-Digital Compute in Memory Accelerator for Deep Learning Workloadscited by 2
  11. 2024StoX-Net: Stochastic Processing of Partial Sums for Efficient In-Memory Computing DNN Acceleratorscited by 2
  12. 2025COMPASS: A Compiler Framework for Resource-Constrained Crossbar-Array Based In-Memory Deep Learning Acceleratorscited by 2
  13. 2025MINIMALIST: switched-capacitor circuits for efficient in-memory computation of gated recurrent unitscited by 2
  14. 2022EcoFlow: Efficient Convolutional Dataflows for Low-Power Neural Network Acceleratorscited by 1
  15. 2022Thermal Heating in ReRAM Crossbar Arrays: Challenges and Solutionscited by 1
  16. 2023TransPimLib: A Library for Efficient Transcendental Functions on Processing-in-Memory Systemscited by 1
  17. 2023IMAC-Sim: A Circuit-level Simulator For In-Memory Analog Computing Architecturescited by 1
  18. 2023Comprehensive Benchmarking of Binary Neural Networks on NVM Crossbar Architecturescited by 1
  19. 2023LRMP: Layer Replication with Mixed Precision for Spatial In-memory DNN Acceleratorscited by 1
  20. 2023RACE-IT: A Reconfigurable Analog Computing Engine for In-Memory Transformer Accelerationcited by 1
  21. 2023WWW: What, When, Where to Compute-in-Memorycited by 1
  22. 2024CLSA-CIM: A Cross-Layer Scheduling Approach for Computing-in-Memory Architecturescited by 1
  23. 2024Multi-Objective Neural Architecture Search for In-Memory Computingcited by 1
  24. 2024Efficient Noise Mitigation for Enhancing Inference Accuracy in DNNs on Mixed-Signal Acceleratorscited by 1
  25. 2024Harnessing Nonidealities in Analog In-Memory Computing Circuits: A Physical Modeling Approach for Neuromorphic Systemscited by 1
  26. 2025Current Opinions on Memristor-Accelerated Machine Learning Hardwarecited by 1
  27. 2025Harmonia: Enhancing Data Placement and Migration in Hybrid Storage Systems via Multi-Agent Reinforcement Learningcited by 1
  28. 2025CIMFlow: An Integrated Framework for Systematic Design and Evaluation of Digital CIM Architecturescited by 1
  29. 2025Memristor-Based Neural Network Accelerators for Space Applications: Enhancing Performance with Temporal Averaging and SIRENscited by 1
  30. 2021On the Noise Stability and Robustness of Adversarially Trained Networks on NVM Crossbarscited by 0
  31. 2021Phantom: A High-Performance Computational Core for Sparse Convolutional Neural Networkscited by 0
  32. 2022NEON: Enabling Efficient Support for Nonlinear Operations in Resistive RAM-based Neural Network Acceleratorscited by 0
  33. 2023ReDy: A Novel ReRAM-centric Dynamic Quantization Approach for Energy-efficient CNN Inferencecited by 0
  34. 2023SupeRBNN: Randomized Binary Neural Network Using Adiabatic Superconductor Josephson Devicescited by 0
  35. 2023A Survey on Design Methodologies for Accelerating Deep Learning on Heterogeneous Architecturescited by 0
  36. 2024Pruning for Improved ADC Efficiency in Crossbar-based Analog In-memory Acceleratorscited by 0
  37. 2024Comparative Evaluation of Memory Technologies for Synaptic Crossbar Arrays- Part 2: Design Knobs and DNN Accuracy Trendscited by 0
  38. 2024Approximate ADCs for In-Memory Computingcited by 0

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