DARTH-PUM: A Hybrid Processing-Using-Memory Architecture
Not on the map. Why?
Abstract (arXiv)
Analog processing-using-memory (PUM; a.k.a. in-memory computing) makes use of electrical interactions inside memory arrays to perform bulk matrix-vector multiplication (MVM) operations. However, many popular matrix-based kernels need to execute non-MVM operations, which analog PUM cannot directly perform. To retain its energy efficiency, analog PUM architectures augment memory arrays with CMOS-based domain-specific fixed-function hardware to provide complete kernel functionality, but the difficulty of integrating such specialized CMOS logic with memory arrays has largely limited analog PUM to being an accelerator for machine learning inference, or for closely related kernels. An opportunity exists to harness analog PUM for general-purpose computation: recent works have shown that memory arrays can also perform Boolean PUM operations, albeit with very different supporting hardware and electrical signals than analog PUM. We propose DARTH-PUM, a general-purpose hybrid PUM architecture that tackles key hardware and software challenges to integrating analog PUM and digital PUM. We propose optimized peripheral circuitry, coordinating hardware to manage and interface between both types of PUM, an easy-to-use programming interface, and low-cost support for flexible data widths. These design elements allow us to build a practical PUM architecture that can execute kernels fully in memory, and can scale easily to cater to domains ranging from embedded applications to large-scale data-driven computing. We show how three popular applications (AES encryption, convolutional neural networks, large language models) can map to and benefit from DARTH-PUM, with speedups of 59.4x, 14.8x, and 40.8x over an analog+CPU baseline.
Key facts. No citing papers in the map yet (data through 7 Oct 2026). Builds on 29 of its 165 references that are in the map. First posted on arXiv 17 Feb 2026.
Builds on
29 of 165 references.
References · 29
- 2015Deep Residual Learning for Image Recognitioncited by 51,809
- 2018BERT: Pre-training of Deep Bidirectional Transformers for Language Understandingcited by 40,204
- 2019PyTorch: An Imperative Style, High-Performance Deep Learning Librarycited by 20,160
- 2023LLaMA: Open and Efficient Foundation Language Modelscited by 13,958
- 2021I-BERT: Integer-only BERT Quantizationcited by 250
- 2019PUMA: A Programmable Ultra-efficient Memristor-based Accelerator for Machine Learning Inferencecited by 57
- 2019RecNMP: Accelerating Personalized Recommendation with Near-Memory Processingcited by 49
- 2021Exploring Transformers in Natural Language Generation: GPT, BERT, and XLNetcited by 27
- 2017GraphR: Accelerating Graph Processing Using ReRAMcited by 19
- 2017Multiscale Co-Design Analysis of Energy, Latency, Area, and Accuracy of a ReRAM Analog Neural Training Acceleratorcited by 15
- 2022Sparse Attention Acceleration with Synergistic In-Memory Pruning and On-Chip Recomputationcited by 12
- 2021DAMOV: A New Methodology and Benchmark Suite for Evaluating Data Movement Bottleneckscited by 10
17 more
- 2021FORMS: Fine-grained Polarized ReRAM-based In-situ Computation for Mixed-signal DNN Acceleratorcited by 10
- 2021QUAC-TRNG: High-Throughput True Random Number Generation Using Quadruple Row Activation in Commodity DRAM Chipscited by 7
- 2023RAELLA: Reforming the Arithmetic for Efficient, Low-Resolution, and Low-Loss Analog PIM: No Retraining Required!cited by 7
- 2018Newton: Gravitating Towards the Physical Limits of Crossbar Accelerationcited by 5
- 2024PIM-Opt: Demystifying Distributed Optimization Algorithms on a Real-World Processing-In-Memory Systemcited by 5
- 2019FPSA: A Full System Stack Solution for Reconfigurable ReRAM-based NN Accelerator Architecturecited by 4
- 2021PiDRAM: A Holistic End-to-end FPGA-based Framework for Processing-in-DRAMcited by 4
- 2025Hybrid SLC-MLC RRAM Mixed-Signal Processing-in-Memory Architecture for Transformer Acceleration via Gradient Redistributioncited by 4
- 2020ReFloat: Low-Cost Floating-Point Processing in ReRAM for Accelerating Iterative Linear Solverscited by 3
- 2022DRAM Bender: An Extensible and Versatile FPGA-based Infrastructure to Easily Test State-of-the-art DRAM Chipscited by 3
- 2020Device-aware inference operations in SONOS nonvolatile memory arrayscited by 2
- 2023OSA-HCIM: On-The-Fly Saliency-Aware Hybrid SRAM CIM with Dynamic Precision Configurationcited by 2
- 2024Functionally-Complete Boolean Logic in Real DRAM Chips: Experimental Characterization and Analysiscited by 2
- 2024HCiM: ADC-Less Hybrid Analog-Digital Compute in Memory Accelerator for Deep Learning Workloadscited by 2
- 2025Multi-Dimensional Vector ISA Extension for Mobile In-Cache Computingcited by 2
- 2024Simultaneous Many-Row Activation in Off-the-Shelf DRAM Chips: Experimental Characterization and Analysiscited by 1
- 2024Analog fast Fourier transforms for scalable and efficient signal processingcited by 1
Built on by
Not cited yet.