Multi-Objective Neural Architecture Search for In-Memory Computing
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Abstract (arXiv)
In this work, we employ neural architecture search (NAS) to enhance the efficiency of deploying diverse machine learning (ML) tasks on in-memory computing (IMC) architectures. Initially, we design three fundamental components inspired by the convolutional layers found in VGG and ResNet models. Subsequently, we utilize Bayesian optimization to construct a convolutional neural network (CNN) model with adaptable depths, employing these components. Through the Bayesian search algorithm, we explore a vast search space comprising over 640 million network configurations to identify the optimal solution, considering various multi-objective cost functions like accuracy/latency and accuracy/energy. Our evaluation of this NAS approach for IMC architecture deployment spans three distinct image classification datasets, demonstrating the effectiveness of our method in achieving a balanced solution characterized by high accuracy and reduced latency and energy consumption.
Key facts. Cited by 1 paper in the map (data through 7 Oct 2026). Builds on 8 of its 27 references that are in the map. First posted on arXiv 10 Jun 2024.
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8 of 27 references.
References · 8
- 2015Deep Residual Learning for Image Recognitioncited by 51,809
- 2019PUMA: A Programmable Ultra-efficient Memristor-based Accelerator for Machine Learning Inferencecited by 57
- 2019Device-Circuit-Architecture Co-Exploration for Computing-in-Memory Neural Acceleratorscited by 32
- 2021Uncertainty Modeling of Emerging Device-based Computing-in-Memory Neural Accelerators with Application to Neural Architecture Searchcited by 17
- 2021An In-Memory Analog Computing Co-Processor for Energy-Efficient CNN Inference on Mobile Devicescited by 9
- 2022Interconnect Parasitics and Partitioning in Fully-Analog In-Memory Computing Architecturescited by 6
- 2023Heterogeneous Integration of In-Memory Analog Computing Architectures with Tensor Processing Unitscited by 4
- 2023IMAC-Sim: A Circuit-level Simulator For In-Memory Analog Computing Architecturescited by 1
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