FORMS: Fine-grained Polarized ReRAM-based In-situ Computation for Mixed-signal DNN Accelerator
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Abstract (arXiv)
Recent works demonstrated the promise of using resistive random access memory (ReRAM) as an emerging technology to perform inherently parallel analog domain in-situ matrix-vector multiplication -- the intensive and key computation in DNNs. With weights stored in the ReRAM crossbar cells as conductance, when the input vector is applied to word lines, the matrix-vector multiplication results can be generated as the current in bit lines. A key problem is that the weight can be either positive or negative, but the in-situ computation assumes all cells on each crossbar column with the same sign. The current architectures either use two ReRAM crossbars for positive and negative weights, or add an offset to weights so that all values become positive. Neither solution is ideal: they either double the cost of crossbars, or incur extra offset circuity. To better solve this problem, this paper proposes FORMS, a fine-grained ReRAM-based DNN accelerator with polarized weights. Instead of trying to represent the positive/negative weights, our key design principle is to enforce exactly what is assumed in the in-situ computation -- ensuring that all weights in the same column of a crossbar have the same sign. It naturally avoids the cost of an additional crossbar. Such weights can be nicely generated using alternating direction method of multipliers (ADMM) regularized optimization, which can exactly enforce certain patterns in DNN weights. To achieve high accuracy, we propose to use fine-grained sub-array columns, which provide a unique opportunity for input zero-skipping, significantly avoiding unnecessary computations. It also makes the hardware much easier to implement. Putting all together, with the same optimized models, FORMS achieves significant throughput improvement and speed up in frame per second over ISAAC with similar area cost.
Key facts. Cited by 10 papers in the map (data through 7 Oct 2026). Builds on 34 of its 84 references that are in the map. First posted on arXiv 16 Jun 2021.
Builds on
34 of 84 references.
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Built on by
Citing papers per year: 2021: 2; 2022: 3; 2023: 1; 2024: 2; 2025: 1; 2026: 1.
10 papers.
- 2022ANT: Exploiting Adaptive Numerical Data Type for Low-bit Deep Neural Network Quantizationcited by 42
- 2022Sparse Attention Acceleration with Synergistic In-Memory Pruning and On-Chip Recomputationcited by 12
- 2021On the Accuracy of Analog Neural Network Inference Acceleratorscited by 9
- 2025RoRA: Efficient Fine-Tuning of LLM with Reliability Optimization for Rank Adaptationcited by 9
- 2021Automatic Mapping of the Best-Suited DNN Pruning Schemes for Real-Time Mobile Accelerationcited by 7
- 2024CIM-MLC: A Multi-level Compilation Stack for Computing-In-Memory Acceleratorscited by 3
- 2024Zero-Space Cost Fault Tolerance for Transformer-based Language Models on ReRAMcited by 2
- 2022Heterogeneous Data-Centric Architectures for Modern Data-Intensive Applications: Case Studies in Machine Learning and Databasescited by 1
- 2023Subgraph Stationary Hardware-Software Inference Co-Designcited by 1
- 2026DARTH-PUM: A Hybrid Processing-Using-Memory Architecturecited by 0
- 2026DARTH-PUM: A Hybrid Processing-Using-Memory Architecture17 Feb 2026
- 2025RoRA: Efficient Fine-Tuning of LLM with Reliability Optimization for Rank Adaptation8 Jan 2025
- 2024CIM-MLC: A Multi-level Compilation Stack for Computing-In-Memory Accelerators23 Jan 2024
- 2024Zero-Space Cost Fault Tolerance for Transformer-based Language Models on ReRAM22 Jan 2024
- 2023Subgraph Stationary Hardware-Software Inference Co-Design21 Jun 2023
- 2022Sparse Attention Acceleration with Synergistic In-Memory Pruning and On-Chip Recomputation1 Sep 2022
- 2022ANT: Exploiting Adaptive Numerical Data Type for Low-bit Deep Neural Network Quantization30 Aug 2022
- 2022Heterogeneous Data-Centric Architectures for Modern Data-Intensive Applications: Case Studies in Machine Learning and Databases29 May 2022
- 2021Automatic Mapping of the Best-Suited DNN Pruning Schemes for Real-Time Mobile Acceleration22 Nov 2021
- 2021On the Accuracy of Analog Neural Network Inference Accelerators3 Sep 2021