X-Former: In-Memory Acceleration of Transformers
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Abstract (arXiv)
Transformers have achieved great success in a wide variety of natural language processing (NLP) tasks due to the attention mechanism, which assigns an importance score for every word relative to other words in a sequence. However, these models are very large, often reaching hundreds of billions of parameters, and therefore require a large number of DRAM accesses. Hence, traditional deep neural network (DNN) accelerators such as GPUs and TPUs face limitations in processing Transformers efficiently. In-memory accelerators based on non-volatile memory promise to be an effective solution to this challenge, since they provide high storage density while performing massively parallel matrix vector multiplications within memory arrays. However, attention score computations, which are frequently used in Transformers (unlike CNNs and RNNs), require matrix vector multiplications (MVM) where both operands change dynamically for each input. As a result, conventional NVM-based accelerators incur high write latency and write energy when used for Transformers, and further suffer from the low endurance of most NVM technologies. To address these challenges, we present X-Former, a hybrid in-memory hardware accelerator that consists of both NVM and CMOS processing elements to execute transformer workloads efficiently. To improve the hardware utilization of X-Former, we also propose a sequence blocking dataflow, which overlaps the computations of the two processing elements and reduces execution time. Across several benchmarks, we show that X-Former achieves upto 85x and 7.5x improvements in latency and energy over a NVIDIA GeForce GTX 1060 GPU and upto 10.7x and 4.6x improvements in latency and energy over a state-of-the-art in-memory NVM accelerator.
Key facts. Cited by 25 papers in the map (data through 14 Oct 2026). Builds on 17 of its 41 references that are in the map. First posted on arXiv 13 Mar 2023.
Builds on
17 of 41 references.
References · 17
- 2017Attention Is All You Needcited by 60,361
- 2018BERT: Pre-training of Deep Bidirectional Transformers for Language Understandingcited by 40,399
- 2020Language Models are Few-Shot Learnerscited by 32,419
- 2018GLUE: A Multi-Task Benchmark and Analysis Platform for Natural Language Understandingcited by 4,899
- 2016SQuAD: 100,000+ Questions for Machine Comprehension of Textcited by 4,148
- 2020Efficient Transformers: A Surveycited by 790
- 2017In-Datacenter Performance Analysis of a Tensor Processing Unitcited by 618
- 2020SpAtten: Efficient Sparse Attention Architecture with Cascade Token and Head Pruningcited by 234
- 2020GOBO: Quantizing Attention-Based NLP Models for Low Latency and Energy Efficient Inferencecited by 106
- 2020A3: Accelerating Attention Mechanisms in Neural Networks with Approximationcited by 101
- 2020EdgeBERT: Sentence-Level Energy Optimizations for Latency-Aware Multi-Task NLP Inferencecited by 70
- 2019PUMA: A Programmable Ultra-efficient Memristor-based Accelerator for Machine Learning Inferencecited by 61
5 more
- 2021Softermax: Hardware/Software Co-Design of an Efficient Softmax for Transformerscited by 54
- 2020Towards Fully 8-bit Integer Inference for the Transformer Modelcited by 35
- 2019PANTHER: A Programmable Architecture for Neural Network Training Harnessing Energy-efficient ReRAMcited by 17
- 2020PoWER-BERT: Accelerating BERT Inference via Progressive Word-vector Eliminationcited by 10
- 2020TxSim:Modeling Training of Deep Neural Networks on Resistive Crossbar Systemscited by 9
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Citing papers per year: 2024: 13; 2025: 9; 2026: 3.
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- 2024Memory Is All You Need: An Overview of Compute-in-Memory Architectures for Accelerating Large Language Model Inference12 Jun 2024
- 2024Efficient Heterogeneous Large Language Model Decoding with Model-Attention Disaggregation3 May 2024
- 2024ClipFormer: Key-Value Clipping of Transformers on Memristive Crossbars for Write Noise Mitigation4 Feb 2024
- 2024A Survey on Hardware Accelerators for Large Language Models18 Jan 2024
- 2024A Survey: Collaborative Hardware and Software Design in the Era of Large Language Modelscited by 23
- 2024A Survey on Hardware Accelerators for Large Language Modelscited by 16
- 2024Memory Is All You Need: An Overview of Compute-in-Memory Architectures for Accelerating Large Language Model Inferencecited by 15
- 2024Efficient Heterogeneous Large Language Model Decoding with Model-Attention Disaggregationcited by 12
- 2024Analog In-Memory Computing Attention Mechanism for Fast and Energy-Efficient Large Language Modelscited by 11
- 2025Low-Cost FlashAttention with Fused Exponential and Multiplication Hardware Operatorscited by 5
- 2024ClipFormer: Key-Value Clipping of Transformers on Memristive Crossbars for Write Noise Mitigationcited by 4
- 2024Hardware Acceleration of LLMs: A comprehensive survey and comparisoncited by 3
- 2024TReX- Reusing Vision Transformer's Attention for Efficient Xbar-based Computingcited by 2
- 2025Atleus: Accelerating Transformers on the Edge Enabled by 3D Heterogeneous Manycore Architecturescited by 2
- 2025HaLoRA: Hardware-aware Low-Rank Adaptation for Large Language Models Based on Hybrid Compute-in-Memory Architecturecited by 2
- 2025FLASH-D: FlashAttention with Hidden Softmax Divisioncited by 2
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- 2025Vectorized FlashAttention with Low-cost Exponential Computation in RISC-V Vector Processors8 Oct 2025
- 2025HALO: Memory-Centric Heterogeneous Accelerator with 2.5D Integration for Low-Batch LLM Inference3 Oct 2025
- 2025AnalogNAS-Bench: A NAS Benchmark for Analog In-Memory Computing23 Jun 2025
- 2025FAR: Function-preserving Attention Replacement for IMC-friendly Inference24 May 2025
- 2025Low-Cost FlashAttention with Fused Exponential and Multiplication Hardware Operators20 May 2025
- 2025FLASH-D: FlashAttention with Hidden Softmax Division20 May 2025
- 2025PIM-LLM: A High-Throughput Hybrid PIM Architecture for 1-bit LLMs31 Mar 2025
- 2025HaLoRA: Hardware-aware Low-Rank Adaptation for Large Language Models Based on Hybrid Compute-in-Memory Architecture27 Feb 2025
- 2025Atleus: Accelerating Transformers on the Edge Enabled by 3D Heterogeneous Manycore Architectures16 Jan 2025
- 2024FLARE: FP-Less PTQ and Low-ENOB ADC Based AMS-PiM for Error-Resilient, Fast, and Efficient Transformer Acceleration22 Nov 2024
12 newest of 23 All 23 (JSON)