mlsanityData to 14 Oct 2026

BF-IMNA: A Bit Fluid In-Memory Neural Architecture for Neural Network Acceleration

arXiv 2411.01417 ↗First posted 3 Nov 2024cs.AR cs.AIcited by 3

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Abstract (arXiv)

Mixed-precision quantization works Neural Networks (NNs) are gaining traction for their efficient realization on the hardware leading to higher throughput and lower energy. In-Memory Computing (IMC) accelerator architectures are offered as alternatives to traditional architectures relying on a data-centric computational paradigm, diminishing the memory wall problem, and scoring high throughput and energy efficiency. These accelerators can support static fixed-precision but are not flexible to support mixed-precision NNs. In this paper, we present BF-IMNA, a bit fluid IMC accelerator for end-to-end Convolutional NN (CNN) inference that is capable of static and dynamic mixed-precision without any hardware reconfiguration overhead at run-time. At the heart of BF-IMNA are Associative Processors (APs), which are bit-serial word-parallel Single Instruction, Multiple Data (SIMD)-like engines. We report the performance of end-to-end inference of ImageNet on AlexNet, VGG16, and ResNet50 on BF-IMNA for different technologies (eNVM and NVM), mixed-precision configurations, and supply voltages. To demonstrate bit fluidity, we implement HAWQ-V3's per-layer mixed-precision configurations for ResNet18 on BF-IMNA using different latency budgets, and results reveal a trade-off between accuracy and Energy-Delay Product (EDP): On one hand, mixed-precision with a high latency constraint achieves the closest accuracy to fixed-precision INT8 and reports a high (worse) EDP compared to fixed-precision INT4. On the other hand, with a low latency constraint, BF-IMNA reports the closest EDP to fixed-precision INT4, with a higher degradation in accuracy compared to fixed-precision INT8. We also show that BF-IMNA with fixed-precision configuration still delivers performance that is comparable to current state-of-the-art accelerators: BF-IMNA achieves 20% higher energy efficiency and 2% higher throughput.

Key facts. Cited by 3 papers in the map (data through 14 Oct 2026). Builds on 20 of its 54 references that are in the map. First posted on arXiv 3 Nov 2024.

Builds on

20 of 54 references.

References · 20

  1. 2015Deep Residual Learning for Image Recognitioncited by 52,096
  2. 2014Very Deep Convolutional Networks for Large-Scale Image Recognitioncited by 15,364
  3. 2017Quantization and Training of Neural Networks for Efficient Integer-Arithmetic-Only Inferencecited by 1,593
  4. 2018HAQ: Hardware-Aware Automated Quantization with Mixed Precisioncited by 443
  5. 2020A Survey of Convolutional Neural Networks: Analysis, Applications, and Prospectscited by 397
  6. 2014Caffe: Convolutional Architecture for Fast Feature Embeddingcited by 288
  7. 2023TPU v4: An Optically Reconfigurable Supercomputer for Machine Learning with Hardware Support for Embeddingscited by 202
  8. 2017Bit Fusion: Bit-Level Dynamically Composable Architecture for Accelerating Deep Neural Networkscited by 109
  9. 2020Data Movement Is All You Need: A Case Study on Optimizing Transformerscited by 108
  10. 2020APQ: Joint Search for Network Architecture, Pruning and Quantization Policycited by 99
  11. 2020Bayesian Bits: Unifying Quantization and Pruningcited by 94
  12. 2019AutoQ: Automated Kernel-Wise Neural Network Quantizationcited by 63
8 more
  1. 2024SliM-LLM: Salience-Driven Mixed-Precision Quantization for Large Language Modelscited by 63
  2. 2019PUMA: A Programmable Ultra-efficient Memristor-based Accelerator for Machine Learning Inferencecited by 61
  3. 2018Edge Intelligence: On-Demand Deep Learning Model Co-Inference with Device-Edge Synergycited by 51
  4. 2020A Survey of Methods for Low-Power Deep Learning and Computer Visioncited by 37
  5. 2017Parallel Multi Channel Convolution using General Matrix Multiplicationcited by 30
  6. 2021Bit-Mixer: Mixed-precision networks with runtime bit-width selectioncited by 22
  7. 2021Resistive Neural Hardware Acceleratorscited by 6
  8. 2022In-memory Associative Processors: Tutorial, Potential, and Challengescited by 6

Built on by

Cited by year (2026 to 14 Oct)

Citing papers per year: 2024: 1; 2025: 1; 2026: 1.

3 papers.

  1. 2025Mixed-Precision Quantization for Language Models: Techniques and Prospectscited by 5
  2. 2024SoftmAP: Software-Hardware Co-design for Integer-Only Softmax on Associative Processorscited by 4
  3. 2026EdgeCIM: A Hardware-Software Co-Design for CIM-Based Acceleration of Small Language Modelscited by 0

Similar, not cited

Close in wording, no citation either way

  1. 2022FAT: An In-Memory Accelerator with Fast Addition for Ternary Weight Neural Networks
  2. 2024Exploring Quantization and Mapping Synergy in Hardware-Aware Deep Neural Network Accelerators
  3. 2025MaRVIn: A Cross-Layer Mixed-Precision RISC-V Framework for DNN Inference, from ISA Extension to Hardware Acceleration
  4. 2024Full-Stack Optimization for CAM-Only DNN Inference
  5. 2023Free Bits: Latency Optimization of Mixed-Precision Quantized Neural Networks on the Edge
  6. 2023MEGA: A Memory-Efficient GNN Accelerator Exploiting Degree-Aware Mixed-Precision Quantization
  7. 2022Design of High-Throughput Mixed-Precision CNN Accelerators on FPGA
  8. 2025Binary Weight Multi-Bit Activation Quantization for Compute-in-Memory CNN Accelerators