MRAM-based Analog Sigmoid Function for In-memory Computing
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Abstract (arXiv)
We propose an analog implementation of the transcendental activation function leveraging two spin-orbit torque magnetoresistive random-access memory (SOT-MRAM) devices and a CMOS inverter. The proposed analog neuron circuit consumes 1.8-27x less power, and occupies 2.5-4931x smaller area, compared to the state-of-the-art analog and digital implementations. Moreover, the developed neuron can be readily integrated with memristive crossbars without requiring any intermediate signal conversion units. The architecture-level analyses show that a fully-analog in-memory computing (IMC) circuit that use our SOT-MRAM neuron along with an SOT-MRAM based crossbar can achieve more than 1.1x, 12x, and 13.3x reduction in power, latency, and energy, respectively, compared to a mixed-signal implementation with analog memristive crossbars and digital neurons. Finally, through cross-layer analyses, we provide a guide on how varying the device-level parameters in our neuron can affect the accuracy of multilayer perceptron (MLP) for MNIST classification.
Key facts. Cited by 4 papers in the map (data through 14 Oct 2026). Builds on 6 of its 26 references that are in the map. First posted on arXiv 21 Apr 2022.
Builds on
6 of 26 references.
References · 6
- 2014Very Deep Convolutional Networks for Large-Scale Image Recognitioncited by 15,364
- 2014Going Deeper with Convolutionscited by 4,241
- 2019PUMA: A Programmable Ultra-efficient Memristor-based Accelerator for Machine Learning Inferencecited by 61
- 2021An In-Memory Analog Computing Co-Processor for Energy-Efficient CNN Inference on Mobile Devicescited by 9
- 2022Interconnect Parasitics and Partitioning in Fully-Analog In-Memory Computing Architecturescited by 6
- 2018Composable Probabilistic Inference Networks Using MRAM-based Stochastic Neuronscited by 2
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Citing papers per year: 2022: 1; 2023: 2; 2024: 0; 2025: 1.
4 papers.
- 2023Heterogeneous Integration of In-Memory Analog Computing Architectures with Tensor Processing Unitscited by 4
- 2023IMAC-Sim: A Circuit-level Simulator For In-Memory Analog Computing Architecturescited by 1
- 2025PIM-LLM: A High-Throughput Hybrid PIM Architecture for 1-bit LLMscited by 1
- 2022Reliability-Aware Deployment of DNNs on In-Memory Analog Computing Architecturescited by 0
- 2025PIM-LLM: A High-Throughput Hybrid PIM Architecture for 1-bit LLMs31 Mar 2025
- 2023Heterogeneous Integration of In-Memory Analog Computing Architectures with Tensor Processing Units18 Apr 2023
- 2023IMAC-Sim: A Circuit-level Simulator For In-Memory Analog Computing Architectures18 Apr 2023
- 2022Reliability-Aware Deployment of DNNs on In-Memory Analog Computing Architectures2 Oct 2022