ForgeEDA: A Comprehensive Multimodal Dataset for Advancing EDA
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Abstract (arXiv)
We introduce ForgeEDA, an open-source comprehensive circuit dataset across various categories. ForgeEDA includes diverse circuit representations such as Register Transfer Level (RTL) code, Post-mapping (PM) netlists, And-Inverter Graphs (AIGs), and placed netlists, enabling comprehensive analysis and development. We demonstrate ForgeEDA's utility by benchmarking state-of-the-art EDA algorithms on critical tasks such as Power, Performance, and Area (PPA) optimization, highlighting its ability to expose performance gaps and drive advancements. Additionally, ForgeEDA's scale and diversity facilitate the training of AI models for EDA tasks, demonstrating its potential to improve model performance and generalization. By addressing limitations in existing datasets, ForgeEDA aims to catalyze breakthroughs in modern IC design and support the next generation of innovations in EDA.
Key facts. Cited by 8 papers in the map (data through 7 Oct 2026). First posted on arXiv 4 May 2025.
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Citing papers per year: 2025: 3; 2026: 5.
8 papers.
- 2025Revolution or Hype? Seeking the Limits of Large Models in Hardware Designcited by 9
- 2025Functional Matching of Logic Subgraphs: Beyond Structural Isomorphismcited by 1
- 2026CapBench: A Multi-PDK Dataset for Machine-Learning-Based Post-Layout Capacitance Extractioncited by 1
- 2026RTL-BenchLS: A Large-Scale Benchmark for RTL Reasoning and Generation with Large Language Modelscited by 1
- 2025TRACE: Learning to Compute on Circuit Graphscited by 0
- 2026GNN-based Path-aware multi-view Circuit Learning for Technology Mappingcited by 0
- 2026R2G: A Multi-View Circuit Graph Benchmark Suite from RTL to GDSIIcited by 0
- 2026CircuitGate: Logic-Consistent Circuit-Level Functional Modeling for And-Inverter Graphscited by 0
- 2026CircuitGate: Logic-Consistent Circuit-Level Functional Modeling for And-Inverter Graphs7 Oct 2026
- 2026RTL-BenchLS: A Large-Scale Benchmark for RTL Reasoning and Generation with Large Language Models8 Jun 2026
- 2026CapBench: A Multi-PDK Dataset for Machine-Learning-Based Post-Layout Capacitance Extraction13 Apr 2026
- 2026R2G: A Multi-View Circuit Graph Benchmark Suite from RTL to GDSII9 Apr 2026
- 2026GNN-based Path-aware multi-view Circuit Learning for Technology Mapping14 Jan 2026
- 2025TRACE: Learning to Compute on Circuit Graphs26 Sep 2025
- 2025Revolution or Hype? Seeking the Limits of Large Models in Hardware Design5 Sep 2025
- 2025Functional Matching of Logic Subgraphs: Beyond Structural Isomorphism28 May 2025