mlsanityData to 14 Oct 2026

CIMNAS: A Joint Framework for Compute-In-Memory-Aware Neural Architecture Search

arXiv 2509.25862 ↗First posted 30 Sep 2025cs.AI cs.AR cs.ETcited by 1

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Abstract (arXiv)

To maximize hardware efficiency and performance accuracy in Compute-In-Memory (CIM)-based neural network accelerators for Artificial Intelligence (AI) applications, co-optimizing both software and hardware design parameters is essential. Manual tuning is impractical due to the vast number of parameters and their complex interdependencies. To effectively automate the design and optimization of CIM-based neural network accelerators, hardware-aware neural architecture search (HW-NAS) techniques can be applied. This work introduces CIMNAS, a joint model-quantization-hardware optimization framework for CIM architectures. CIMNAS simultaneously searches across software parameters, quantization policies, and a broad range of hardware parameters, incorporating device-, circuit-, and architecture-level co-optimizations. CIMNAS experiments were conducted over a search space of 9.9x10^85 potential parameter combinations with the MobileNet model as a baseline and RRAM-based CIM architecture. Evaluated on the ImageNet dataset, CIMNAS achieved a reduction in energy-delay-area product (EDAP) ranging from 90.1x to 104.5x, an improvement in TOPS/W between 4.68x and 4.82x, and an enhancement in TOPS/mm^2 from 11.3x to 12.78x relative to various baselines, all while maintaining an accuracy of 73.81%. The adaptability and robustness of CIMNAS are demonstrated by extending the framework to support the SRAM-based ResNet50 architecture, achieving up to an 819.5x reduction in EDAP. Unlike other state-of-the-art methods, CIMNAS achieves EDAP-focused optimization without any accuracy loss, generating diverse software-hardware parameter combinations for high-performance CIM-based neural network designs. The source code of CIMNAS is available at https://github.com/OlgaKrestinskaya/CIMNAS.

Key facts. Cited by 1 paper in the map (data through 14 Oct 2026). Builds on 24 of its 54 references that are in the map. First posted on arXiv 30 Sep 2025.

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24 of 54 references.

References · 24

  1. 2018MobileNetV2: Inverted Residuals and Linear Bottleneckscited by 4,795
  2. 2018DARTS: Differentiable Architecture Searchcited by 1,798
  3. 2017Learning Transferable Architectures for Scalable Image Recognitioncited by 1,101
  4. 2018MnasNet: Platform-Aware Neural Architecture Search for Mobilecited by 943
  5. 2019Once-for-All: Train One Network and Specialize it for Efficient Deploymentcited by 787
  6. 2020A Comprehensive Survey of Neural Architecture Search: Challenges and Solutionscited by 254
  7. 2020pymoo: Multi-objective Optimization in Pythoncited by 200
  8. 2019BANANAS: Bayesian Optimization with Neural Architectures for Neural Architecture Searchcited by 179
  9. 2020APQ: Joint Search for Network Architecture, Pruning and Quantization Policycited by 99
  10. 2020DNN+NeuroSim V2.0: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators for On-chip Trainingcited by 33
  11. 2020Breaking the Curse of Space Explosion: Towards Efficient NAS with Curriculum Searchcited by 33
  12. 2019Device-Circuit-Architecture Co-Exploration for Computing-in-Memory Neural Acceleratorscited by 32
12 more
  1. 2021Uncertainty Modeling of Emerging Device-based Computing-in-Memory Neural Accelerators with Application to Neural Architecture Searchcited by 17
  2. 2021Multi-Objective Optimization of ReRAM Crossbars for Robust DNN Inferencing under Stochastic Noisecited by 12
  3. 2024Roadmap to Neuromorphic Computing with Emerging Technologiescited by 12
  4. 2021FLASH: Fast Neural Architecture Search with Hardware Optimizationcited by 11
  5. 2023AnalogNAS: A Neural Network Design Framework for Accurate Inference with Analog In-Memory Computingcited by 10
  6. 2024CiMLoop: A Flexible, Accurate, and Fast Compute-In-Memory Modeling Toolcited by 10
  7. 2021AnalogNets: ML-HW Co-Design of Noise-robust TinyML Models and Always-On Analog Compute-in-Memory Acceleratorcited by 7
  8. 2021Resistive Neural Hardware Acceleratorscited by 6
  9. 2023XPert: Peripheral Circuit & Neural Architecture Co-search for Area and Energy-efficient Xbar-based Computingcited by 6
  10. 2023Towards Efficient In-memory Computing Hardware for Quantized Neural Networks: State-of-the-art, Open Challenges and Perspectivescited by 5
  11. 2024Towards Efficient IMC Accelerator Design Through Joint Hardware-Workload Co-optimizationcited by 2
  12. 2024NASH: Neural Architecture and Accelerator Search for Multiplication-Reduced Hybrid Modelscited by 1

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Cited by year (2026 to 14 Oct)

Citing papers per year: 2026: 1.

1 paper.

  1. 2026Joint Hardware-Workload Co-Optimization for In-Memory Computing Acceleratorscited by 0

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  1. 2025CIMPool: Scalable Neural Network Acceleration for Compute-In-Memory using Weight Pools
  2. 2025Optimizing Binary and Ternary Neural Network Inference on RRAM Crossbars using CIM-Explorer
  3. 2024Full-Stack Optimization for CAM-Only DNN Inference
  4. 2022HQNAS: Auto CNN deployment framework for joint quantization and architecture search
  5. 2026ChatNeuroSim: An LLM Agent Framework for Automated Compute-in-Memory Accelerator Deployment and Optimization
  6. 2025A Hybrid-Domain Floating-Point Compute-in-Memory Architecture for Efficient Acceleration of High-Precision Deep Neural Networks ↗
  7. 2026Mixed-Precision Training and Compilation for RRAM-based Computing-in-Memory Accelerators
  8. 2021HAO: Hardware-aware neural Architecture Optimization for Efficient Inference