XPert: Peripheral Circuit & Neural Architecture Co-search for Area and Energy-efficient Xbar-based Computing
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Abstract (arXiv)
The hardware-efficiency and accuracy of Deep Neural Networks (DNNs) implemented on In-memory Computing (IMC) architectures primarily depend on the DNN architecture and the peripheral circuit parameters. It is therefore essential to holistically co-search the network and peripheral parameters to achieve optimal performance. To this end, we propose XPert, which co-searches network architecture in tandem with peripheral parameters such as the type and precision of analog-to-digital converters, crossbar column sharing and the layer-specific input precision using an optimization-based design space exploration. Compared to VGG16 baselines, XPert achieves 10.24x (4.7x) lower EDAP, 1.72x (1.62x) higher TOPS/W,1.93x (3x) higher TOPS/mm2 at 92.46% (56.7%) accuracy for CIFAR10 (TinyImagenet) datasets. The code for this paper is available at https://github.com/Intelligent-Computing-Lab-Yale/XPert.
Key facts. Cited by 6 papers in the map (data through 14 Oct 2026). Builds on 3 of its 18 references that are in the map. First posted on arXiv 30 Mar 2023.
Builds on
3 of 18 references.
References · 3
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Citing papers per year: 2024: 3; 2025: 2; 2026: 1.
6 papers.
- 2024TReX- Reusing Vision Transformer's Attention for Efficient Xbar-based Computingcited by 2
- 2024Towards Efficient IMC Accelerator Design Through Joint Hardware-Workload Co-optimizationcited by 2
- 2024When In-memory Computing Meets Spiking Neural Networks -- A Perspective on Device-Circuit-System-and-Algorithm Co-designcited by 1
- 2025CIMNAS: A Joint Framework for Compute-In-Memory-Aware Neural Architecture Searchcited by 1
- 2025Computing-In-Memory Aware Model Adaption For Edge Devicescited by 0
- 2026Joint Hardware-Workload Co-Optimization for In-Memory Computing Acceleratorscited by 0
- 2026Joint Hardware-Workload Co-Optimization for In-Memory Computing Accelerators4 Mar 2026
- 2025Computing-In-Memory Aware Model Adaption For Edge Devices16 Oct 2025
- 2025CIMNAS: A Joint Framework for Compute-In-Memory-Aware Neural Architecture Search30 Sep 2025
- 2024Towards Efficient IMC Accelerator Design Through Joint Hardware-Workload Co-optimization22 Oct 2024
- 2024When In-memory Computing Meets Spiking Neural Networks -- A Perspective on Device-Circuit-System-and-Algorithm Co-design22 Aug 2024
- 2024TReX- Reusing Vision Transformer's Attention for Efficient Xbar-based Computing22 Aug 2024