mlsanityData to 14 Oct 2026

Towards Efficient IMC Accelerator Design Through Joint Hardware-Workload Co-optimization

arXiv 2410.16759 ↗First posted 22 Oct 2024cs.AR cs.AIcited by 2

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Abstract (arXiv)

Designing generalized in-memory computing (IMC) hardware that efficiently supports a variety of workloads requires extensive design space exploration, which is infeasible to perform manually. Optimizing hardware individually for each workload or solely for the largest workload often fails to yield the most efficient generalized solutions. To address this, we propose a joint hardware-workload optimization framework that identifies optimised IMC chip architecture parameters, enabling more efficient, workload-flexible hardware. We show that joint optimization achieves 36%, 36%, 20%, and 69% better energy-latency-area scores for VGG16, ResNet18, AlexNet, and MobileNetV3, respectively, compared to the separate architecture parameters search optimizing for a single largest workload. Additionally, we quantify the performance trade-offs and losses of the resulting generalized IMC hardware compared to workload-specific IMC designs.

Key facts. Cited by 2 papers in the map (data through 14 Oct 2026). Builds on 14 of its 38 references that are in the map. First posted on arXiv 22 Oct 2024.

Builds on

14 of 38 references.

References · 14

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2 more
  1. 2023XPert: Peripheral Circuit & Neural Architecture Co-search for Area and Energy-efficient Xbar-based Computingcited by 6
  2. 2023Towards Efficient In-memory Computing Hardware for Quantized Neural Networks: State-of-the-art, Open Challenges and Perspectivescited by 5

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Cited by year (2026 to 14 Oct)

Citing papers per year: 2025: 1; 2026: 1.

2 papers.

  1. 2025CIMNAS: A Joint Framework for Compute-In-Memory-Aware Neural Architecture Searchcited by 1
  2. 2026Joint Hardware-Workload Co-Optimization for In-Memory Computing Acceleratorscited by 0