Multi-Objective Optimization of ReRAM Crossbars for Robust DNN Inferencing under Stochastic Noise
Not on the map. Why?
Abstract (arXiv)
Resistive random-access memory (ReRAM) is a promising technology for designing hardware accelerators for deep neural network (DNN) inferencing. However, stochastic noise in ReRAM crossbars can degrade the DNN inferencing accuracy. We propose the design and optimization of a high-performance, area-and energy-efficient ReRAM-based hardware accelerator to achieve robust DNN inferencing in the presence of stochastic noise. We make two key technical contributions. First, we propose a stochastic-noise-aware training method, referred to as ReSNA, to improve the accuracy of DNN inferencing on ReRAM crossbars with stochastic noise. Second, we propose an information-theoretic algorithm, referred to as CF-MESMO, to identify the Pareto set of solutions to trade-off multiple objectives, including inferencing accuracy, area overhead, execution time, and energy consumption. The main challenge in this context is that executing the ReSNA method to evaluate each candidate ReRAM design is prohibitive. To address this challenge, we utilize the continuous-fidelity evaluation of ReRAM designs associated with prohibitive high computation cost by varying the number of training epochs to trade-off accuracy and cost. CF-MESMO iteratively selects the candidate ReRAM design and fidelity pair that maximizes the information gained per unit computation cost about the optimal Pareto front. Our experiments on benchmark DNNs show that the proposed algorithms efficiently uncover high-quality Pareto fronts. On average, ReSNA achieves 2.57% inferencing accuracy improvement for ResNet20 on the CIFAR-10 dataset with respect to the baseline configuration. Moreover, CF-MESMO algorithm achieves 90.91% reduction in computation cost compared to the popular multi-objective optimization algorithm NSGA-II to reach the best solution from NSGA-II.
Key facts. Cited by 12 papers in the map (data through 7 Oct 2026). Builds on 9 of its 52 references that are in the map. First posted on arXiv 12 Sep 2021.
Builds on
9 of 52 references.
References · 9
- 2015Deep Residual Learning for Image Recognitioncited by 51,809
- 2014Very Deep Convolutional Networks for Large-Scale Image Recognitioncited by 15,267
- 2015Deep Compression: Compressing Deep Neural Networks with Pruning, Trained Quantization and Huffman Codingcited by 2,291
- 2016DoReFa-Net: Training Low Bitwidth Convolutional Neural Networks with Low Bitwidth Gradientscited by 557
- 2017Multi-fidelity Bayesian Optimisation with Continuous Approximationscited by 120
- 2020Max-value Entropy Search for Multi-Objective Bayesian Optimization with Constraintscited by 81
- 2021BSQ: Exploring Bit-Level Sparsity for Mixed-Precision Neural Network Quantizationcited by 37
- 2019Trading-off Accuracy and Energy of Deep Inference on Embedded Systems: A Co-Design Approachcited by 8
- 2019RED: A ReRAM-based Deconvolution Acceleratorcited by 2
Built on by
Citing papers per year: 2022: 2; 2023: 2; 2024: 2; 2025: 3; 2026: 3.
12 papers.
- 2022Approximate Computing and the Efficient Machine Learning Expeditioncited by 8
- 2023Preference-Aware Constrained Multi-Objective Bayesian Optimizationcited by 4
- 2024Towards Efficient IMC Accelerator Design Through Joint Hardware-Workload Co-optimizationcited by 2
- 2025Atleus: Accelerating Transformers on the Edge Enabled by 3D Heterogeneous Manycore Architecturescited by 2
- 2022Thermal Heating in ReRAM Crossbar Arrays: Challenges and Solutionscited by 1
- 2023TransCODE: Co-design of Transformers and Accelerators for Efficient Training and Inferencecited by 1
- 2025CIMNAS: A Joint Framework for Compute-In-Memory-Aware Neural Architecture Searchcited by 1
- 2025End-to-End Transformer Acceleration Through Processing-in-Memory Architecturescited by 1
- 2026QMC: Efficient SLM Edge Inference via Outlier-Aware Quantization and Emergent Memories Co-Designcited by 1
- 2024Non-Myopic Multi-Objective Bayesian Optimizationcited by 0
- 2026Joint Hardware-Workload Co-Optimization for In-Memory Computing Acceleratorscited by 0
- 2026ThRIve: Thermally Robust CNN Inference via Low-Rank Adaptation in Heterogeneous PIM Architecturescited by 0
- 2026ThRIve: Thermally Robust CNN Inference via Low-Rank Adaptation in Heterogeneous PIM Architectures19 Jul 2026
- 2026Joint Hardware-Workload Co-Optimization for In-Memory Computing Accelerators4 Mar 2026
- 2026QMC: Efficient SLM Edge Inference via Outlier-Aware Quantization and Emergent Memories Co-Design21 Jan 2026
- 2025End-to-End Transformer Acceleration Through Processing-in-Memory Architectures21 Nov 2025
- 2025CIMNAS: A Joint Framework for Compute-In-Memory-Aware Neural Architecture Search30 Sep 2025
- 2025Atleus: Accelerating Transformers on the Edge Enabled by 3D Heterogeneous Manycore Architectures16 Jan 2025
- 2024Non-Myopic Multi-Objective Bayesian Optimization11 Dec 2024
- 2024Towards Efficient IMC Accelerator Design Through Joint Hardware-Workload Co-optimization22 Oct 2024
- 2023TransCODE: Co-design of Transformers and Accelerators for Efficient Training and Inference27 Mar 2023
- 2023Preference-Aware Constrained Multi-Objective Bayesian Optimization23 Mar 2023
- 2022Thermal Heating in ReRAM Crossbar Arrays: Challenges and Solutions28 Dec 2022
- 2022Approximate Computing and the Efficient Machine Learning Expedition2 Oct 2022