Resistive Neural Hardware Accelerators
Not on the map. Why?
Abstract (arXiv)
Deep Neural Networks (DNNs), as a subset of Machine Learning (ML) techniques, entail that real-world data can be learned and that decisions can be made in real-time. However, their wide adoption is hindered by a number of software and hardware limitations. The existing general-purpose hardware platforms used to accelerate DNNs are facing new challenges associated with the growing amount of data and are exponentially increasing the complexity of computations. An emerging non-volatile memory (NVM) devices and processing-in-memory (PIM) paradigm is creating a new hardware architecture generation with increased computing and storage capabilities. In particular, the shift towards ReRAM-based in-memory computing has great potential in the implementation of area and power efficient inference and in training large-scale neural network architectures. These can accelerate the process of the IoT-enabled AI technologies entering our daily life. In this survey, we review the state-of-the-art ReRAM-based DNN many-core accelerators, and their superiority compared to CMOS counterparts was shown. The review covers different aspects of hardware and software realization of DNN accelerators, their present limitations, and future prospectives. In particular, comparison of the accelerators shows the need for the introduction of new performance metrics and benchmarking standards. In addition, the major concerns regarding the efficient design of accelerators include a lack of accuracy in simulation tools for software and hardware co-design.
Key facts. Cited by 6 papers in the map (data through 14 Oct 2026). First posted on arXiv 8 Sep 2021.
Builds on
No reference list yet.
Built on by
Citing papers per year: 2022: 1; 2023: 0; 2024: 3; 2025: 1; 2026: 1.
6 papers.
- 2024BF-IMNA: A Bit Fluid In-Memory Neural Architecture for Neural Network Accelerationcited by 3
- 2024Towards Efficient IMC Accelerator Design Through Joint Hardware-Workload Co-optimizationcited by 2
- 2022Thermal Heating in ReRAM Crossbar Arrays: Challenges and Solutionscited by 1
- 2025CIMNAS: A Joint Framework for Compute-In-Memory-Aware Neural Architecture Searchcited by 1
- 2024Full-Stack Optimization for CAM-Only DNN Inferencecited by 0
- 2026Joint Hardware-Workload Co-Optimization for In-Memory Computing Acceleratorscited by 0
- 2026Joint Hardware-Workload Co-Optimization for In-Memory Computing Accelerators4 Mar 2026
- 2025CIMNAS: A Joint Framework for Compute-In-Memory-Aware Neural Architecture Search30 Sep 2025
- 2024BF-IMNA: A Bit Fluid In-Memory Neural Architecture for Neural Network Acceleration3 Nov 2024
- 2024Towards Efficient IMC Accelerator Design Through Joint Hardware-Workload Co-optimization22 Oct 2024
- 2024Full-Stack Optimization for CAM-Only DNN Inference23 Jan 2024
- 2022Thermal Heating in ReRAM Crossbar Arrays: Challenges and Solutions28 Dec 2022