SIRA: Scaled-Integer Range Analysis for Optimizing FPGA Dataflow Neural Network Accelerators

arXiv 2508.21493 ↗First posted 29 Aug 2025cs.ARcited by 0

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Abstract (arXiv)

While neural network quantization effectively reduces the cost of matrix multiplications, aggressive quantization can expose non-matrix-multiply operations as significant performance and resource bottlenecks on embedded systems. Addressing such bottlenecks requires a comprehensive approach to tailoring the precision across operations in the inference computation. To this end, we introduce scaled-integer range analysis (SIRA), a static analysis technique employing interval arithmetic to determine the range, scale, and bias for tensors in quantized neural networks. We show how this information can be exploited to reduce the resource footprint of FPGA dataflow neural network accelerators via tailored bitwidth adaptation for accumulators and downstream operations, aggregation of scales and biases, and conversion of consecutive elementwise operations to thresholding operations. We integrate SIRA-driven optimizations into the open-source FINN framework, then evaluate their effectiveness across a range of quantized neural network workloads and compare implementation alternatives for non-matrix-multiply operations. We demonstrate an average reduction of 17% for LUTs, 66% for DSPs, and 22% for accumulator bitwidths with SIRA optimizations, providing detailed benchmark analysis and analytical models to guide the implementation style for non-matrix layers. Finally, we open-source SIRA to facilitate community exploration of its benefits across various applications and hardware platforms.

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References · 21

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2024MagR: Weight Magnitude Reduction for Enhancing Post-Training Quantizationcited by 28
2019EPIC: An Energy-Efficient, High-Performance GPGPU Computing Research Infrastructurecited by 23

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2022RAPQ: Rescuing Accuracy for Power-of-Two Low-bit Post-training Quantizationcited by 15
2017Streamlined Deployment for Quantized Neural Networkscited by 12
2023A2Q: Accumulator-Aware Quantization with Guaranteed Overflow Avoidancecited by 12
2022QONNX: Representing Arbitrary-Precision Quantized Neural Networkscited by 10
2020HPIPE: Heterogeneous Layer-Pipelined and Sparse-Aware CNN Inference for FPGAscited by 7
2024Accumulator-Aware Post-Training Quantization for Large Language Modelscited by 6
2024PikeLPN: Mitigating Overlooked Inefficiencies of Low-Precision Neural Networkscited by 4
2024Understanding the Performance Horizon of the Latest ML Workloads with NonGEMM Workloadscited by 4
2023End-to-end codesign of Hessian-aware quantized neural networks for FPGAs and ASICscited by 2

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