PikeLPN: Mitigating Overlooked Inefficiencies of Low-Precision Neural Networks
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Abstract (arXiv)
Low-precision quantization is recognized for its efficacy in neural network optimization. Our analysis reveals that non-quantized elementwise operations which are prevalent in layers such as parameterized activation functions, batch normalization, and quantization scaling dominate the inference cost of low-precision models. These non-quantized elementwise operations are commonly overlooked in SOTA efficiency metrics such as Arithmetic Computation Effort (ACE). In this paper, we propose ACEv2 - an extended version of ACE which offers a better alignment with the inference cost of quantized models and their energy consumption on ML hardware. Moreover, we introduce PikeLPN, a model that addresses these efficiency issues by applying quantization to both elementwise operations and multiply-accumulate operations. In particular, we present a novel quantization technique for batch normalization layers named QuantNorm which allows for quantizing the batch normalization parameters without compromising the model performance. Additionally, we propose applying Double Quantization where the quantization scaling parameters are quantized. Furthermore, we recognize and resolve the issue of distribution mismatch in Separable Convolution layers by introducing Distribution-Heterogeneous Quantization which enables quantizing them to low-precision. PikeLPN achieves Pareto-optimality in efficiency-accuracy trade-off with up to 3X efficiency improvement compared to SOTA low-precision models.
Key facts. Cited by 4 papers in the map (data through 14 Oct 2026). Builds on 33 of its 54 references that are in the map. First posted on arXiv 29 Mar 2024.
Builds on
33 of 54 references.
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21 more
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Citing papers per year: 2024: 1; 2025: 1; 2026: 2.
4 papers.
- 2024Robust Training of Neural Networks at Arbitrary Precision and Sparsitycited by 3
- 2026LogicIR: Logic Gate Networks for Image Restorationcited by 1
- 2025SIRA: Scaled-Integer Range Analysis for Optimizing FPGA Dataflow Neural Network Acceleratorscited by 0
- 2026Overcoming Kernel Redundancy for Scaling Logic Gate Networkscited by 0
- 2026Overcoming Kernel Redundancy for Scaling Logic Gate Networks1 Oct 2026
- 2026LogicIR: Logic Gate Networks for Image Restoration25 Jun 2026
- 2025SIRA: Scaled-Integer Range Analysis for Optimizing FPGA Dataflow Neural Network Accelerators29 Aug 2025
- 2024Robust Training of Neural Networks at Arbitrary Precision and Sparsity14 Sep 2024
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- 2021A White Paper on Neural Network Quantization
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