FPSA: A Full System Stack Solution for Reconfigurable ReRAM-based NN Accelerator Architecture
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Abstract (arXiv)
Neural Network (NN) accelerators with emerging ReRAM (resistive random access memory) technologies have been investigated as one of the promising solutions to address the textitmemory wall challenge, due to the unique capability of textitprocessing-in-memory within ReRAM-crossbar-based processing elements (PEs). However, the high efficiency and high density advantages of ReRAM have not been fully utilized due to the huge communication demands among PEs and the overhead of peripheral circuits. In this paper, we propose a full system stack solution, composed of a reconfigurable architecture design, Field Programmable Synapse Array (FPSA) and its software system including neural synthesizer, temporal-to-spatial mapper, and placement & routing. We highly leverage the software system to make the hardware design compact and efficient. To satisfy the high-performance communication demand, we optimize it with a reconfigurable routing architecture and the placement & routing tool. To improve the computational density, we greatly simplify the PE circuit with the spiking schema and then adopt neural synthesizer to enable the high density computation-resources to support different kinds of NN operations. In addition, we provide spiking memory blocks (SMBs) and configurable logic blocks (CLBs) in hardware and leverage the temporal-to-spatial mapper to utilize them to balance the storage and computation requirements of NN. Owing to the end-to-end software system, we can efficiently deploy existing deep neural networks to FPSA. Evaluations show that, compared to one of state-of-the-art ReRAM-based NN accelerators, PRIME, the computational density of FPSA improves by 31x; for representative NNs, its inference performance can achieve up to 1000x speedup.
Key facts. Cited by 4 papers in the map (data through 14 Oct 2026). First posted on arXiv 28 Jan 2019.
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Citing papers per year: 2021: 1; 2022: 1; 2023: 0; 2024: 1; 2025: 0; 2026: 1.
4 papers.
- 2021Bring Your Own Codegen to Deep Learning Compilercited by 5
- 2024CIM-MLC: A Multi-level Compilation Stack for Computing-In-Memory Acceleratorscited by 3
- 2022NEON: Enabling Efficient Support for Nonlinear Operations in Resistive RAM-based Neural Network Acceleratorscited by 0
- 2026DARTH-PUM: A Hybrid Processing-Using-Memory Architecturecited by 0
- 2026DARTH-PUM: A Hybrid Processing-Using-Memory Architecture17 Feb 2026
- 2024CIM-MLC: A Multi-level Compilation Stack for Computing-In-Memory Accelerators23 Jan 2024
- 2022NEON: Enabling Efficient Support for Nonlinear Operations in Resistive RAM-based Neural Network Accelerators10 Nov 2022
- 2021Bring Your Own Codegen to Deep Learning Compiler3 May 2021