QUAC-TRNG: High-Throughput True Random Number Generation Using Quadruple Row Activation in Commodity DRAM Chips
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Abstract (arXiv)
True random number generators (TRNG) sample random physical processes to create large amounts of random numbers for various use cases, including security-critical cryptographic primitives, scientific simulations, machine learning applications, and even recreational entertainment. Unfortunately, not every computing system is equipped with dedicated TRNG hardware, limiting the application space and security guarantees for such systems. To open the application space and enable security guarantees for the overwhelming majority of computing systems that do not necessarily have dedicated TRNG hardware, we develop QUAC-TRNG. QUAC-TRNG exploits the new observation that a carefully-engineered sequence of DRAM commands activates four consecutive DRAM rows in rapid succession. This QUadruple ACtivation (QUAC) causes the bitline sense amplifiers to non-deterministically converge to random values when we activate four rows that store conflicting data because the net deviation in bitline voltage fails to meet reliable sensing margins. We experimentally demonstrate that QUAC reliably generates random values across 136 commodity DDR4 DRAM chips from one major DRAM manufacturer. We describe how to develop an effective TRNG (QUAC-TRNG) based on QUAC. We evaluate the quality of our TRNG using NIST STS and find that QUAC-TRNG successfully passes each test. Our experimental evaluations show that QUAC-TRNG generates true random numbers with a throughput of 3.44 Gb/s (per DRAM channel), outperforming the state-of-the-art DRAM-based TRNG by 15.08x and 1.41x for basic and throughput-optimized versions, respectively. We show that QUAC-TRNG utilizes DRAM bandwidth better than the state-of-the-art, achieving up to 2.03x the throughput of a throughput-optimized baseline when scaling bus frequencies to 12 GT/s.
Key facts. Cited by 7 papers in the map (data through 7 Oct 2026). First posted on arXiv 19 May 2021.
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Citing papers per year: 2022: 4; 2023: 1; 2024: 0; 2025: 1; 2026: 1.
7 papers.
- 2022Machine Learning Training on a Real Processing-in-Memory Systemcited by 4
- 2022Accelerating Neural Network Inference with Processing-in-DRAM: From the Edge to the Cloudcited by 4
- 2022An Experimental Evaluation of Machine Learning Training on a Real Processing-in-Memory Systemcited by 2
- 2022Heterogeneous Data-Centric Architectures for Modern Data-Intensive Applications: Case Studies in Machine Learning and Databasescited by 1
- 2023TransPimLib: A Library for Efficient Transcendental Functions on Processing-in-Memory Systemscited by 1
- 2025EIM-TRNG: Obfuscating Deep Neural Network Weights with Encoding-in-Memory True Random Number Generator via RowHammercited by 0
- 2026DARTH-PUM: A Hybrid Processing-Using-Memory Architecturecited by 0
- 2026DARTH-PUM: A Hybrid Processing-Using-Memory Architecture17 Feb 2026
- 2025EIM-TRNG: Obfuscating Deep Neural Network Weights with Encoding-in-Memory True Random Number Generator via RowHammer3 Jul 2025
- 2023TransPimLib: A Library for Efficient Transcendental Functions on Processing-in-Memory Systems3 Apr 2023
- 2022Accelerating Neural Network Inference with Processing-in-DRAM: From the Edge to the Cloud19 Sep 2022
- 2022An Experimental Evaluation of Machine Learning Training on a Real Processing-in-Memory System16 Jul 2022
- 2022Machine Learning Training on a Real Processing-in-Memory System13 Jun 2022
- 2022Heterogeneous Data-Centric Architectures for Modern Data-Intensive Applications: Case Studies in Machine Learning and Databases29 May 2022