mlsanityData to 14 Oct 2026

Advancing Routing-Awareness in Analog ICs Floorplanning

arXiv 2510.15387 ↗First posted 17 Oct 2025cs.AI cs.LGcited by 0

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Abstract (arXiv)

The adoption of machine learning-based techniques for analog integrated circuit layout, unlike its digital counterpart, has been limited by the stringent requirements imposed by electric and problem-specific constraints, along with the interdependence of floorplanning and routing steps. In this work, we address a prevalent concern among layout engineers regarding the need for readily available routing-aware floorplanning solutions. To this extent, we develop an automatic floorplanning engine based on reinforcement learning and relational graph convolutional neural network specifically tailored to condition the floorplan generation towards more routable outcomes. A combination of increased grid resolution and precise pin information integration, along with a dynamic routing resource estimation technique, allows balancing routing and area efficiency, eventually meeting industrial standards. When analyzing the place and route effectiveness in a simulated environment, the proposed approach achieves a 13.8% reduction in dead space, a 40.6% reduction in wirelength and a 73.4% increase in routing success when compared to past learning-based state-of-the-art techniques.

Key facts. No citing papers in the map yet (data through 14 Oct 2026). Builds on 9 of its 33 references that are in the map. First posted on arXiv 17 Oct 2025.

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9 of 33 references.

References · 9

  1. 2015U-Net: Convolutional Networks for Biomedical Image Segmentationcited by 19,713
  2. 2017Proximal Policy Optimization Algorithmscited by 15,215
  3. 2017Modeling Relational Data with Graph Convolutional Networkscited by 1,694
  4. 2014Learning to Executecited by 106
  5. 2022MaskPlace: Fast Chip Placement via Reinforced Visual Representation Learningcited by 43
  6. 2023ChiPFormer: Transferable Chip Placement via Offline Decision Transformercited by 42
  7. 2020ALIGN: A System for Automating Analog Layoutcited by 8
  8. 2024Effective Analog ICs Floorplanning with Relational Graph Neural Networks and Reinforcement Learningcited by 5
  9. 2023Toward Reinforcement Learning-based Rectilinear Macro Placement Under Human Constraintscited by 2

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  1. 2024Fast ML-driven Analog Circuit Layout using Reinforcement Learning and Steiner Trees
  2. 2025Enhancing Reinforcement Learning for the Floorplanning of Analog ICs with Beam Search
  3. 2026RulePlanner: All-in-One Reinforcement Learner for Unifying Design Rules in 3D Floorplanning
  4. 2026Validity-Preserving Hierarchical RL for Joint Routing and Switch Placement in EDA
  5. 2024Automated Placement of Analog Integrated Circuits using Priority-based Constructive Heuristic ↗
  6. 2026OSIRIS: Bridging Analog Circuit Design and Machine Learning with Scalable Dataset Generation
  7. 2025Late Breaking Results: Breaking Symmetry- Unconventional Placement of Analog Circuits using Multi-Level Multi-Agent Reinforcement Learning
  8. 2026Simulation-Aware In-Context Policy Improvement for LLM-Aided Analog Layout Refinement