Toward Reinforcement Learning-based Rectilinear Macro Placement Under Human Constraints
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Abstract (arXiv)
Macro placement is a critical phase in chip design, which becomes more intricate when involving general rectilinear macros and layout areas. Furthermore, macro placement that incorporates human-like constraints, such as design hierarchy and peripheral bias, has the potential to significantly reduce the amount of additional manual labor required from designers. This study proposes a methodology that leverages an approach suggested by Google's Circuit Training (G-CT) to provide a learning-based macro placer that not only supports placing rectilinear cases, but also adheres to crucial human-like design principles. Our experimental results demonstrate the effectiveness of our framework in achieving power-performance-area (PPA) metrics and in obtaining placements of high quality, comparable to those produced with human intervention. Additionally, our methodology shows potential as a generalized model to address diverse macro shapes and layout areas.
Key facts. Cited by 2 papers in the map (data through 7 Oct 2026). Builds on 3 of its 26 references that are in the map. First posted on arXiv 3 Nov 2023.
Builds on
3 of 26 references.
References · 3
- 2017Proximal Policy Optimization Algorithmscited by 14,441
- 2021On Joint Learning for Solving Placement and Routing in Chip Designcited by 44
- 2022MaskPlace: Fast Chip Placement via Reinforced Visual Representation Learningcited by 43
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Citing papers per year: 2024: 1; 2025: 1.
2 papers.